On Jan 21, 8:14=A0pm, whygee <why...@yg.yg> wrote:> Brian Drummond wrote: > > The other fine grained one was of course Xilinx's own XC6200, originall=y> > developed in Edinburgh by Algotronics (bought out by Xilinx). Much love=d> > by researchers because every detail of configuration and routing was > > made public; if there was ever a chance of a completely open-source > > toolchain, that was it. I believe the basic unit of logic was a 4-LUT > > and FF, nothing fancy. > > Oh, that is an interesting topic ! > > I have been told that today, 90% of the investments of FPGA vendors > go to SW design. Open Source is maybe a solution, since it has evolved > a lot in the last years. Though I know pretty well that current Open Sour=ce EDA> tools suck. But I would like to think in the long term. > And with all those oooold FPGA-related patents going to the public domain=,> new opportunities appear, unlike 5 or 10 years ago... > > > Consider that with current FPGAs, the area occupied by logic is dwarfed > > by the routing area. With fine grained logic that problem must be about > > an order of magnitude worse. Factor in the optimisation opportunities > > that more complex logic blocks give you; from hard-wired fast carry > > chains all the way up to multipliers or DSP units, and you can see why > > the trend is towards coarser grained logic. > > I have read that 4-LUT based ASICs with metal-layer customisation > are faster and denser, for this reason : interco transistors that > take roughly 80% of the surface are reduced a lot. > Something I have learnt only recently... > > > I would expect to see basic units like 8-bit blocks, > > almost PLD-like ? > > > with enough > > resources that you could fit a Z80 into half a dozen, in a generation o=r> > two. Forty thousand of them, as well as the block memory, I/O, DSP and =a> > few ARMs or PPCs to supervise the lot. > > One annoying thing is that I see a lot of families with multipliers. > why don't they simply provide adders too ? > multiplies take a lot of resources, sure, but adders are everywhere... > > > Time to dig out the old bit-slice databooks again? > > History rhymes again :-) > > Thanks for the insights, > > > - Brian > > yg > > --http://ygdes.com/http://yasep.orghm, maybe i should sell my ERA6000 ICE pod on ebay? yes that the plessey/pilkington sea of gates FPGA Antti
Actel IGLOO FPGA has lower power consumption then Xilinx Coolrunner-II CPLD?
Started by ●September 3, 2007
Reply by ●January 21, 20092009-01-21
Reply by ●January 21, 20092009-01-21
On Jan 21, 1:14=A0pm, whygee <why...@yg.yg> wrote:> Brian Drummond wrote: > > The other fine grained one was of course Xilinx's own XC6200, originall=y> > developed in Edinburgh by Algotronics (bought out by Xilinx). Much love=d> > by researchers because every detail of configuration and routing was > > made public; if there was ever a chance of a completely open-source > > toolchain, that was it. I believe the basic unit of logic was a 4-LUT > > and FF, nothing fancy. > > Oh, that is an interesting topic ! > > I have been told that today, 90% of the investments of FPGA vendors > go to SW design. Open Source is maybe a solution, since it has evolved > a lot in the last years. Though I know pretty well that current Open Sour=ce EDA> tools suck. But I would like to think in the long term. > And with all those oooold FPGA-related patents going to the public domain=,> new opportunities appear, unlike 5 or 10 years ago... > > > Consider that with current FPGAs, the area occupied by logic is dwarfed > > by the routing area. With fine grained logic that problem must be about > > an order of magnitude worse. Factor in the optimisation opportunities > > that more complex logic blocks give you; from hard-wired fast carry > > chains all the way up to multipliers or DSP units, and you can see why > > the trend is towards coarser grained logic. > > I have read that 4-LUT based ASICs with metal-layer customisation > are faster and denser, for this reason : interco transistors that > take roughly 80% of the surface are reduced a lot. > Something I have learnt only recently...Are you comparing ASICs to FGPAs? I believe that is the basis of the various ASICs available from the FPGA vendors. They just replace the programmable parts with wire. I guess in the case of LUTs that can be used like RAM, they still have to use RAM based LUTs, but they are initialized by metal rather than a bit stream.> > I would expect to see basic units like 8-bit blocks, > > almost PLD-like ?I wonder if things like the 6-LUT can be accommodated in the software by treating it as a set of 4-LUTs with very limited routing? I assume the routing details are fully table driven or something similar in the software.> > with enough > > resources that you could fit a Z80 into half a dozen, in a generation o=r> > two. Forty thousand of them, as well as the block memory, I/O, DSP and =a> > few ARMs or PPCs to supervise the lot. > > One annoying thing is that I see a lot of families with multipliers. > why don't they simply provide adders too ? > multiplies take a lot of resources, sure, but adders are everywhere...They do offer adders. Each bit uses one LUT. That seems pretty cheap to me...> > Time to dig out the old bit-slice databooks again? > > History rhymes again :-) > > Thanks for the insights,Rick
Reply by ●January 21, 20092009-01-21
On Jan 21, 12:45=A0pm, whygee <why...@yg.yg> wrote:> Jonathan Bromley wrote: > > On Tue, 20 Jan 2009 21:45:05 -0800 (PST), rickman wrote: > > >> There was another company called Plus Logic but I really just can't > >> recall the structure of their devices. =A0But I'm pretty sure they > >> wern't 4 LUTs. > > I believe they had a CPLD-like structure. =A0They were absorbed > > by ??Altera after achieving some reasonable sales. > > The bottom ofhttp://www.fpga-guide.com/overview/overview.htmlsays it is X=ilinx.> > BTW, it seems that CPLD-based FPGA are not very succsessful > (and I wouldn't use them unless paid really really well). > > OTOH has anybody read about the "upcoming" memristor-based FPGA ?No, I have not read about this. But the stuff I have read about memristors indicates they are some years away from commercial application. Rick
Reply by ●January 21, 20092009-01-21
Antti wrote:> hm, > > maybe i should sell my > > ERA6000 ICE pod on ebay? > > yes that the plessey/pilkington sea of gates FPGAthat is valuable to so few people... but pictures and a small webpage would be useful for more people :-)> AnttiYG -- http://ygdes.com / http://yasep.org
Reply by ●January 21, 20092009-01-21
rickman wrote:> On Jan 21, 1:14 pm, whygee <why...@yg.yg> wrote: >> why don't they simply provide adders too ? >> multiplies take a lot of resources, sure, but adders are everywhere... > They do offer adders. Each bit uses one LUT. That seems pretty cheap to me...I meant 16-bit or 32-bit adders. How many 4-LUTs does it take to add 32 bits _fast_ ? Not 32...> Rickyg -- http://ygdes.com / http://yasep.org
Reply by ●January 21, 20092009-01-21
rickman wrote:> On Jan 21, 12:45 pm, whygee <why...@yg.yg> wrote: >> OTOH has anybody read about the "upcoming" memristor-based FPGA ? > No, I have not read about this. But the stuff I have read about > memristors indicates they are some years away from commercial > application.Sure. I don't want to be too old to use them when they become available :-) Xilinx seems to use to buy things and swallow companies, maybe they'll get a hint and speed things up this way ?> Rickyg -- http://ygdes.com / http://yasep.org
Reply by ●January 21, 20092009-01-21
On Jan 20, 9:45=A0pm, rickman <gnu...@gmail.com> wrote: [.. snip ..] OK rickman, you've apparently been around for awhile if you can remember all these. :-)> Atmel is a forgotten FPGA vendor. =A0They still sell an FPGA with an AVR > included. =A0This is based on their second generation FPGA with a > (single) 3 input LUT, IIRC.[.. snip ..] The product line is/was called FPSLIC. http://www.atmel.com/products/FPSLIC/ IIRC, the FPSLIC fabric is based off the earlier Concurrent Logic architecture, although my feeble memory might be fooling me.> > Another forgotten vendor is Motorola, most likely because their > product was stillborn. =A0I seem to recall that it was *very* fine > grained although I can't say I ever read any details. =A0I believe they > called it "Crosspoint" or "Crossfield" or something like that.[.. snip ..] This one was called CORE+ based on Motorola's ColdFire processor. I was working a company called Triscend that was doing something similar, but with 8051 and ARM7 coupled with a coarse-grained FPGA fabric. We were worried about CORE+ due to Motorola's market presence, the feature set, and Motorola's stated low, low price. http://findarticles.com/p/articles/mi_m0EKF/is_n2206_v44/ai_20323848 The FPGA fabric was just OK. It was another incarnation of the Pilkington fine-grained architecture. Pilkington, if nothing else, were the world's best FPGA salespeople. They sold the same architecture to the likes of Toshiba, Motorola, and others that I can't now remember.> There was another company called Plus Logic but I really just can't > recall the structure of their devices. =A0But I'm pretty sure they > wern't 4 LUTs.You are correct in that Plus+Logic did not use a 4LUT. They actually became Xilinx' CPLD division during the last great industry consolodation. http://findarticles.com/p/articles/mi_m0EKF/is_n1895_v38/ai_11874375 -- Steve Knapp Prevailing Technology, Inc. www.prevailing-technology.com
Reply by ●January 21, 20092009-01-21
On Wed, 21 Jan 2009 09:03:59 -0800 (PST), rickman <gnuarm@gmail.com> wrote:>On Jan 21, 8:00�am, Brian Drummond <brian_drumm...@btconnect.com> >wrote: >> >> Consider that with current FPGAs, the area occupied by logic is dwarfed >> by the routing area. With fine grained logic that problem must be about >> an order of magnitude worse.>I don't think that is anything new. Back when the XC4000 was new I >was told that "We sell you the routing and give you the logic for >free". >That was the quote. I suspect it's at least equally true today and still driving the balance point.>> I would expect to see basic units like 8-bit blocks, with enough >> resources that you could fit a Z80 into half a dozen, in a generation or >> two. Forty thousand of them, as well as the block memory, I/O, DSP and a >> few ARMs or PPCs to supervise the lot. > >Personally, I would like to see larger functional units as that would >reduce the complexity of the routing fabric. But I think it would be >too much of an impact on the software to properly utilize it >effectively. I am sure this will come, but not in the next few >years. Then again, doesn't the Stradix use 6-LUTs?Maybe, I haven't really kept abreast of the Altera line. - Brian
Reply by ●January 21, 20092009-01-21
On Wed, 21 Jan 2009 19:14:12 +0100, whygee <whygee@yg.yg> wrote:> >> I would expect to see basic units like 8-bit blocks, >almost PLD-like ?Heh, I almost suggested the 22V10 as a candidate for a basic block! 40000 of them could be interesting but I don't want to dust off my CUPL manual for thah...>One annoying thing is that I see a lot of families with multipliers. >why don't they simply provide adders too ? >multiplies take a lot of resources, sure, but adders are everywhere...Essentially every LUT is already part of an adder about as fast as they can make them; I suspect an adder alone would be too small a "grain" to be worthwhile. But the mults now have an accretion of accumulators and other low level facilities around them, so maybe someone is listening to you. In the V5 there are partial adaptations towards supporting single-precision floats; full support might be another useful addition... - Brian
Reply by ●January 22, 20092009-01-22
On Jan 21, 6:24 pm, whygee <why...@yg.yg> wrote:> rickman wrote: > > On Jan 21, 1:14 pm, whygee <why...@yg.yg> wrote: > >> why don't they simply provide adders too ? > >> multiplies take a lot of resources, sure, but adders are everywhere... > > They do offer adders. Each bit uses one LUT. That seems pretty cheap to me... > > I meant 16-bit or 32-bit adders. > How many 4-LUTs does it take to add 32 bits _fast_ ? > Not 32...I don't know just how fast a 32 bit adder from 32 LUTs will run and I don't know how fast a 32 bit hard adder will run. I do know that the long path is the carry chain and this has been highly optimized in most FPGAs. Do you know numbers? The only "fast" adder I know about is a propagate/generate design. If this is implemented using 4-LUTs I believe it will use log2(n) levels and n-1 LUTs in addition to the adder. So a 32 bit adder would use 64 LUTs (32 + 31 + 1 more to produce the final carry out if needed). I can't say much about how fast this circuit would be because the carry chain is very fast and the LUTs are rather slow. Even if you compare 6 levels of LUTs I expect 32 levels of carry will be faster. If you get to 64 bit, perhaps 7 levels of LUTs may be faster but I would not bet on it. Rick
