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Basic questions about the Nios II.

Started by NickNitro September 27, 2007
Hello.

I'm getting a better outline of what's available and the differences
between the different options, such as FPGAs and CPLDs. Although, I've
just come across Alteras "Nios II Embedded Processor" and to be honest
it's thrown me off completely.

- What is a soft-core processor?
- It seems that Nios II isn't a physical product I buy, it appears to
be an emulator running on top of any FPGA (Stratix, Cyclone etc...)?
- Programming the Nios II is done through the Nios II IDE, although
this uses C/C++? Is this then converted into a netlist (along with the
Nios core) to run on a certain FPGA?
- Does using Nios II mean a reduction in performance in comparison to
an FPGA/CPLD?

Thank you.
Nick.

On Sep 27, 7:34 am, NickNitro <NickHo...@googlemail.com> wrote:
> Hello. > > I'm getting a better outline of what's available and the differences > between the different options, such as FPGAs and CPLDs. Although, I've > just come across Alteras "Nios II Embedded Processor" and to be honest > it's thrown me off completely. > > - What is a soft-core processor?
A synthesizable implementation of a processor microarchitecture, probably at the RT level. It is supposed to be targetable across different technologies (FPGAs and or standard cell ASICs).
> - It seems that Nios II isn't a physical product I buy, it appears to > be an emulator running on top of any FPGA (Stratix, Cyclone etc...)?
It is a soft-core processor written in the VHDL hardware description language.
> - Programming the Nios II is done through the Nios II IDE, although > this uses C/C++? Is this then converted into a netlist (along with the > Nios core) to run on a certain FPGA?
As Nios-II is a processor, you can use standard ways to program (HLL down to object code or assembly down to object code). The program memory is kept within the embedded block memories of the FPGA or could be SRAM, SDRAM etc storage.
> - Does using Nios II mean a reduction in performance in comparison to > an FPGA/CPLD?
It means that it is a way to bind the available FPGA resources to do something for you.
> > Thank you. > Nick.
You are welcome. Do you come from a COTS (commercial-off-the-shelf) discipline? Your enquiries are archetypical of this kind of engineers (or students).
On Sep 27, 6:08 am, Uncle Noah <nk...@skiathos.physics.auth.gr> wrote:
<snip>

>>It is supposed to be targetable across different technologies (FPGAs and or standard cell ASICs).
Ok, that clears quite a bit up!
>>It is a soft-core processor written in the VHDL hardware description language.
So essentially I'm buying the 'blueprint' as it were for a RISC processor.
>>It means that it is a way to bind the available FPGA resources to do something for you.
Ok, again that clears much up. But programming my algorithms in VHDL then placing them on an FGPA would result in far superior than using the Nios II core? It is probably a 'how long is a piece of string' type of question, but what performance penalties are there in using the Nios II core in comparison to direct VHDL programming?
>>Do you come from a COTS (commercial-off-the-shelf) discipline?
If that refers to a software engineer (typically for me ASM & C/C++), then yes. :) Thanks again, Nick.
Sorry, I forgot to add how does the C2H fit into the Nios architecture?

> >>It means that it is a way to bind the available FPGA resources to do something for you. > > Ok, again that clears much up. But programming my algorithms in VHDL > then placing them on an FGPA would result in far superior than using > the Nios II core? It is probably a 'how long is a piece of string' > type of question, but what performance penalties are there in using > the Nios II core in comparison to direct VHDL programming?
If you mean that you are thinking of designing customized hardware for a single purpose (let's say one algorithm) and take advantage of the vast parallelism available in FPGAs, then yes, you can get a far superior than a given soft-core processor. Then again, it is possible that the soft-core lets you "communicate" to your piece of hardware and put it under software control without losing too much.
> Thanks again, > Nick.
You are welcome.
On Sep 27, 8:34 am, NickNitro <NickHo...@googlemail.com> wrote:
> Sorry, I forgot to add how does the C2H fit into the Nios architecture?
I believe that you mark a C procedure for hardware implementation. Then the C2H would generate legitimate VHDL for that procedure. Of course it should be carefully written in a C subset or use some form of intrinsics to make this work.
On Sep 27, 6:50 am, Uncle Noah <nk...@skiathos.physics.auth.gr> wrote:
> On Sep 27, 8:34 am, NickNitro <NickHo...@googlemail.com> wrote: > > > Sorry, I forgot to add how does the C2H fit into the Nios architecture? > > I believe that you mark a C procedure for hardware implementation. > Then the C2H would generate legitimate VHDL for that procedure. Of > course it should be carefully written in a C subset or use some form > of intrinsics to make this work.
Why is Nios required for C2H if C2H creates VHDL code?
> > I believe that you mark a C procedure for hardware implementation. > > Then the C2H would generate legitimate VHDL for that procedure. Of > > course it should be carefully written in a C subset or use some form > > of intrinsics to make this work. > > Why is Nios required for C2H if C2H creates VHDL code?
It seems to only be accessible under the Nios-II IDE. Maybe the C2H generates VHDL with taking a certain interface to Nios-II into account. That does not mean that the VHDL generated is not generic (in the sense of needing some strange libraries).
On Sep 27, 7:24 am, Uncle Noah <nk...@skiathos.physics.auth.gr> wrote:
> > > I believe that you mark a C procedure for hardware implementation. > > > Then the C2H would generate legitimate VHDL for that procedure. Of > > > course it should be carefully written in a C subset or use some form > > > of intrinsics to make this work. > > > Why is Nios required for C2H if C2H creates VHDL code? > > It seems to only be accessible under the Nios-II IDE. Maybe the C2H > generates VHDL with taking a certain interface to Nios-II into > account. That does not mean that the VHDL generated is not generic (in > the sense of needing some strange libraries).
Ok wonderful. Thanks for all your help, it is much appreciated. (-: Nick.
>Ok, again that clears much up. But programming my algorithms in VHDL >then placing them on an FGPA would result in far superior than using >the Nios II core? It is probably a 'how long is a piece of string' >type of question, but what performance penalties are there in using >the Nios II core in comparison to direct VHDL programming?
If a state machine gets really complicated, it's often easier/simpler to turn it into a software problem. Usually, "complicated" means lots of states. Sometimes it can be lots of things to do each cycle. In that case, think of a wide instruction rather than a typical RISC instruction. That sort of software is often called microcode. I haven't worked with Nios. I assume it's a reasonably typical software environment. Software is often easier to change/fix/manage and it's often easier to hire software people than hardware people. (Though a web designer type software person isn't likely to be useful on this sort of software.) -- These are my opinions, not necessarily my employer's. I hate spam.