2 leg crystal on FPGA: Lattice vs Xilinx

Hi

I know many wise men has said NO NO, but

1)
http://www.latticesemi.com/forums/forum/messageview.cfm?catid=42&threadid=3505

Lattice engineer suggest that it works (assumable reliable) on machXO

the IO technology between machXO and Xilinx FPGAs isnt so big so I
wonder why cant it be done with Xilinx ?

for what I see is following

25MHz crystal
27p caps
560 series
1M parallel

when using LVCMOS33 SLEW=FAST

then there is some sort of overdrive, that makes oscillation to
periodically stop and restart
200 us work then 75 idle, then restarts again, the FPGA input sees
however nice 25MHz
from the crystal ALL time, (also when the output doesnt swing)

by simply changing slew=slow the circuit does start work reliable.

so any technical reasons why this circuit can not (should not) be
used??

crystal vs oscillator price difference is still some 0.30 USD, so why
waste the pennies

Antti

Antti,

The circuit works, only because the IO acts like an inverter with a very
small delay.

If the IO has more delay, than the circiut will not start up (always).

We do not recommend the use of a crystal like this, as we have
experience that it doesn't always start up.

Will it work once?  Sure.  Will it works always, nope.

I suppose Lattice isn't large enough to worry...

Austin

Antti wrote:
> Hi
> 
> I know many wise men has said NO NO, but
> 
> 1)
> http://www.latticesemi.com/forums/forum/messageview.cfm?catid=42&threadid=3505
> 
> Lattice engineer suggest that it works (assumable reliable) on machXO
> 
> the IO technology between machXO and Xilinx FPGAs isnt so big so I
> wonder why cant it be done with Xilinx ?
> 
> for what I see is following
> 
> 25MHz crystal
> 27p caps
> 560 series
> 1M parallel
> 
> when using LVCMOS33 SLEW=FAST
> 
> then there is some sort of overdrive, that makes oscillation to
> periodically stop and restart
> 200 us work then 75 idle, then restarts again, the FPGA input sees
> however nice 25MHz
> from the crystal ALL time, (also when the output doesnt swing)
> 
> by simply changing slew=slow the circuit does start work reliable.
> 
> so any technical reasons why this circuit can not (should not) be
> used??
> 
> crystal vs oscillator price difference is still some 0.30 USD, so why
> waste the pennies
> 
> Antti
> 

Austin

Might be worth making the suggestion to your sister grouping of GPD of
adding a dedicated oscillator crcuit to their range of products. Given
a lot of micros do that already there would be some logic in adding
such a circuit in the future to the low cost sector FPGA families.

John Adair
Enterpoint Ltd.

On 28 Sep, 21:21, austin <aus...@xilinx.com> wrote:
> Antti,
>
> The circuit works, only because the IO acts like an inverter with a very
> small delay.
>
> If the IO has more delay, than the circiut will not start up (always).
>
> We do not recommend the use of a crystal like this, as we have
> experience that it doesn't always start up.
>
> Will it work once?  Sure.  Will it works always, nope.
>
> I suppose Lattice isn't large enough to worry...
>
> Austin
>
>
>
> Antti wrote:
> > Hi
>
> > I know many wise men has said NO NO, but
>
> > 1)
> >http://www.latticesemi.com/forums/forum/messageview.cfm?catid=42&thre...
>
> > Lattice engineer suggest that it works (assumable reliable) on machXO
>
> > the IO technology between machXO and Xilinx FPGAs isnt so big so I
> > wonder why cant it be done with Xilinx ?
>
> > for what I see is following
>
> > 25MHz crystal
> > 27p caps
> > 560 series
> > 1M parallel
>
> > when using LVCMOS33 SLEW=FAST
>
> > then there is some sort of overdrive, that makes oscillation to
> > periodically stop and restart
> > 200 us work then 75 idle, then restarts again, the FPGA input sees
> > however nice 25MHz
> > from the crystal ALL time, (also when the output doesnt swing)
>
> > by simply changing slew=slow the circuit does start work reliable.
>
> > so any technical reasons why this circuit can not (should not) be
> > used??
>
> > crystal vs oscillator price difference is still some 0.30 USD, so why
> > waste the pennies
>
> > Antti- Hide quoted text -
>
> - Show quoted text -

On Sep 28, 5:05 pm, John Adair <g...@enterpoint.co.uk> wrote:
> Austin
>
> Might be worth making the suggestion to your sister grouping of GPD of
> adding a dedicated oscillator crcuit to their range of products. Given
> a lot of micros do that already there would be some logic in adding
> such a circuit in the future to the low cost sector FPGA families.
>
John, "been there, done that".
XC3000 used to have a single-stage dedicated inverter, exactly for
that purpose. It caused us a lot of support grief. Between 32 kHz and
100 MHz, there is a big variation in xtals, and there also was a
sensitivity to Vcc ramp-up rate. Nobody wants a circuit to work "most
of the time".
I also remember that many of the Intel mask revisions of the 8051 were
oscillator-related. (We second-sourced that at AMD)
My advice has always been: spend a few pennies on an oscillator
circuit made by specialists for a special purpose. And definitely do
not abuse a multi-stage I/O circuit to be the xtal inverter circuit.
Far too much gain and uncontrolled phase changes at very high
frequencies.
Peter Alfke

On Sep 28, 11:30 am, Antti <Antti.Luk...@googlemail.com> wrote:
> Hi
>
> I know many wise men has said NO NO, but
>
> 1)http://www.latticesemi.com/forums/forum/messageview.cfm?catid=42&thre...
>
> Lattice engineer suggest that it works (assumable reliable) on machXO
>
> the IO technology between machXO and Xilinx FPGAs isnt so big so I
> wonder why cant it be done with Xilinx ?
>
> for what I see is following
>
> 25MHz crystal
> 27p caps
> 560 series
> 1M parallel
>
> when using LVCMOS33 SLEW=FAST

This structure works with *any* kind of logic if you understand it has
a pure analogic behaviour and you treat it as a sensitive analogic
stuff (and not a digital one like most software guys do).
The key for a stable oscillation are the crystal parameters and the
value of the output capacitor connected to ground. A small one will
increase the oscillation amplitude and decrease the stability. A very
big one will increase the stability (and the start-up time) and
decrease the amplitude below the gate thresold voltage. None of those
situations are good. The input capacitor can be adjusted up to 50%
without significant changes.
If you plan a mass production, I suggest a variable capacitor of
5-25pF in parallel with a 12pF-20pF (replacing the fixed output
capacitor) for the first board and a carefully observation of the
amplitude at different ambiant temperatures using a good scope and a
10:1 probe.
However, the question "why using a crystal" still remains.

Vasile

vasile wrote:

> On Sep 28, 11:30 am, Antti <Antti.Luk...@googlemail.com> wrote:
>> Hi
>>
>> I know many wise men has said NO NO, but
>>
>> 1)http://www.latticesemi.com/forums/forum/messageview.cfm?catid=42&thre...
>>
>> Lattice engineer suggest that it works (assumable reliable) on machXO
>>
>> the IO technology between machXO and Xilinx FPGAs isnt so big so I
>> wonder why cant it be done with Xilinx ?
>>
>> for what I see is following
>>
>> 25MHz crystal
>> 27p caps
>> 560 series
>> 1M parallel
>>
>> when using LVCMOS33 SLEW=FAST
> 
> This structure works with *any* kind of logic if you understand it has a
> pure analogic behaviour and you treat it as a sensitive analogic stuff
> (and not a digital one like most software guys do).

Well, no. Back when I was quite a bit younger, I tried to build a stable
oscillator with a unused gate on a TTL 7414, with is an inverter with
hysteresis. Tried all sorts of values of capacitors and resisters, and the
best I was able to do was to usually generate the third harmonic.
Sometimes the fifth, sometimes some other multiple of the crystal
frequency, sometimes not a stable frequency, and sometimes even the
frequency of the crystal. Switched to using a 7404, a plain inverter, and
then making a stable oscillator was easy.


-- 
Phil Hays

>Well, no. Back when I was quite a bit younger, I tried to build a stable
>oscillator with a unused gate on a TTL 7414, with is an inverter with
>hysteresis. Tried all sorts of values of capacitors and resisters, and the
>best I was able to do was to usually generate the third harmonic.
>Sometimes the fifth, sometimes some other multiple of the crystal
>frequency, sometimes not a stable frequency, and sometimes even the
>frequency of the crystal. Switched to using a 7404, a plain inverter, and
>then making a stable oscillator was easy.

Did you put it into production and ship a million of them?


They used to make 74U04, U for unbuffered.  It was intended for
hacks like this.

-- 
These are my opinions, not necessarily my employer's.  I hate spam.

On 29 Sep., 02:05, John Adair <g...@enterpoint.co.uk> wrote:
> Austin
>
> Might be worth making the suggestion to your sister grouping of GPD of
> adding a dedicated oscillator crcuit to their range of products. Given
> a lot of micros do that already there would be some logic in adding
> such a circuit in the future to the low cost sector FPGA families.
>
> John Adair
> Enterpoint Ltd.
>

I have submitted this idea (at least 1 DCM with pins for crystal) many
years ago.

Antti

>I have submitted this idea (at least 1 DCM with pins for crystal) many
>years ago.

I assume Xilinx marketing is smart enough to analyze the tradeoffs.

I remember being grumpy that the 2 special IOBs on the 3000 series
chips were slightly different.  I don't remember the details, it
was probably something like slightly slower or a few extra pF.
It wasn't a big deal, at least most of the time, but it was
one more thing you had to keep in mind.

Southbridge chips often contain the RTC and whatever it takes
to drive a 32 KHz crystal.  I haven't looked carefully, but I
haven't seen one that includes the magic PLL clock generator
stuff.  That seems like a very tempting target for high volume
cost sensitive applications so I assume there is a good reason
they don't do it.

-- 
These are my opinions, not necessarily my employer's.  I hate spam.

On 29 Sep., 09:29, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal
Murray) wrote:
> >I have submitted this idea (at least 1 DCM with pins for crystal) many
> >years ago.
>
> I assume Xilinx marketing is smart enough to analyze the tradeoffs.
>
> I remember being grumpy that the 2 special IOBs on the 3000 series
> chips were slightly different.  I don't remember the details, it
> was probably something like slightly slower or a few extra pF.
> It wasn't a big deal, at least most of the time, but it was
> one more thing you had to keep in mind.
>
> Southbridge chips often contain the RTC and whatever it takes
> to drive a 32 KHz crystal.  I haven't looked carefully, but I
> haven't seen one that includes the magic PLL clock generator
> stuff.  That seems like a very tempting target for high volume
> cost sensitive applications so I assume there is a good reason
> they don't do it.
>
> --

well, is that the same reason why Actel _INCLUDED_ oscillator in the
Fusion :) ?

Antti