A small clock synchronization challenge with Virtex E

Greetings, this is my first posting to this group, but I've been
following the discussions for some time.

I have a small problem which I'm trying to solve:

My design has a Virtex E, and I need to generate a 1MHz clock and a
4MHz clock from a single clock source. The are to be used internally
and they need to be synchronized. My problem is that the CLKDLLE
primitive needs a CLKIN of at least 25MHz. I can supply that, I have
an external oscillator tunable from 0 (or very low at least) to 40MHz.
But the CLKDLLE can divide by 16 at maximum, thus I cannot use it to
create the 1MHz clock.

Do I have any options? Are there any other techniques I may apply to
perform division and get a minimal clock skew between the two clocks?

What would happen if I tried to use a CLKIN of 16MHz? No DLL lock?

Thank you,
-Geir Botterli

Use a single clock for the FPGA.
Use enables to clock the 4 MHz flops and/or the 1 MHz flops at every nth (or
4*n-th) edge.
One simple clock.
No DLL.
All flops synchronous with no skew.
Apply the multi-cycle constraint through the enables to get your timing at 4
MHz or 1 MHz.
A thing of beauty.


"Geir Botterli" <geirb@fokk.org> wrote in message
news:308520dbkbv5fm4m3h0ap35n21rrgbqn8e@4ax.com...
> Greetings, this is my first posting to this group, but I've been
> following the discussions for some time.
>
> I have a small problem which I'm trying to solve:
>
> My design has a Virtex E, and I need to generate a 1MHz clock and a
> 4MHz clock from a single clock source. The are to be used internally
> and they need to be synchronized. My problem is that the CLKDLLE
> primitive needs a CLKIN of at least 25MHz. I can supply that, I have
> an external oscillator tunable from 0 (or very low at least) to 40MHz.
> But the CLKDLLE can divide by 16 at maximum, thus I cannot use it to
> create the 1MHz clock.
>
> Do I have any options? Are there any other techniques I may apply to
> perform division and get a minimal clock skew between the two clocks?
>
> What would happen if I tried to use a CLKIN of 16MHz? No DLL lock?
>
> Thank you,
> -Geir Botterli

Rather than using two clocks, clock the whole design with your 4 MHz clock
and then generate a clock enable every 4th clock and feed it to the
flip-flops that have the 1 MHz clocking requirement.  If these are for
output clocks, you could use an 8 MHz clock, and a state machine to
generate the outputs at 1 MHz and 4 MHz.

Geir Botterli wrote:

> Greetings, this is my first posting to this group, but I've been
> following the discussions for some time.
>
> I have a small problem which I'm trying to solve:
>
> My design has a Virtex E, and I need to generate a 1MHz clock and a
> 4MHz clock from a single clock source. The are to be used internally
> and they need to be synchronized. My problem is that the CLKDLLE
> primitive needs a CLKIN of at least 25MHz. I can supply that, I have
> an external oscillator tunable from 0 (or very low at least) to 40MHz.
> But the CLKDLLE can divide by 16 at maximum, thus I cannot use it to
> create the 1MHz clock.
>
> Do I have any options? Are there any other techniques I may apply to
> perform division and get a minimal clock skew between the two clocks?
>
> What would happen if I tried to use a CLKIN of 16MHz? No DLL lock?
>
> Thank you,
> -Geir Botterli

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

"John_H" <johnhandwork@mail.com> wrote in message
<dcyUb.24$uo1.18709@news-west.eli.net> :

Hi, John, thanks for your reply.

>Use a single clock for the FPGA.
>Use enables to clock the 4 MHz flops and/or the 1 MHz flops at every nth (or
>4*n-th) edge.

I'm afraid I don't get how I should use clock enables to achieve this.
The only "solution" i have come up with is like this:

always @ (posedge clk_4MHz)
  clk_2MHz <= ~clk_2MHz;

always @ (posedge clk_2MHz)
  clk_1MHz <= ~clk_1MHz;

+BUFGs

But this will result in a skew between the edges of the 4 and 1 MHz
clocks.

I could run the 4 MHz clock through some logic to delay it, but I
don't like that option very much.

Could you give an example on how to do this with clock enables?

>One simple clock.
>No DLL.
>All flops synchronous with no skew.
>Apply the multi-cycle constraint through the enables to get your timing at 4
>MHz or 1 MHz.
>A thing of beauty.

Sounds wonderful :)

Regards,
-Geir Botterli

Here is an example of how to use "clock enables".

The example uses one of the count states as the "emable"
Variable a will be updated every 4th 4Mhz clock (at a 1Mhz
interval).

always @ (posedge 4Mhz)
begin
  cnt[1:0] <= cnt[1:0] + 1;

  if (cnt == 3) a <= b;
 else a <= b;
end

"Geir Botterli" <geirb@fokk.org> wrote in message
news:16o920li0tfoia1qq0hpm4bbl9sj6krha1@4ax.com...
> "John_H" <johnhandwork@mail.com> wrote in message
> <dcyUb.24$uo1.18709@news-west.eli.net> :
>
> Hi, John, thanks for your reply.
>
> >Use a single clock for the FPGA.
> >Use enables to clock the 4 MHz flops and/or the 1 MHz flops at every nth
(or
> >4*n-th) edge.
>
> I'm afraid I don't get how I should use clock enables to achieve this.
> The only "solution" i have come up with is like this:
>
> always @ (posedge clk_4MHz)
>   clk_2MHz <= ~clk_2MHz;
>
> always @ (posedge clk_2MHz)
>   clk_1MHz <= ~clk_1MHz;
>
> +BUFGs
>
> But this will result in a skew between the edges of the 4 and 1 MHz
> clocks.
>
> I could run the 4 MHz clock through some logic to delay it, but I
> don't like that option very much.
>
> Could you give an example on how to do this with clock enables?
>
> >One simple clock.
> >No DLL.
> >All flops synchronous with no skew.
> >Apply the multi-cycle constraint through the enables to get your timing
at 4
> >MHz or 1 MHz.
> >A thing of beauty.
>
> Sounds wonderful :)
>
> Regards,
> -Geir Botterli
>
>

damn typo ... that should be "else a <= a"

"Mike Lewis" <someone@microsoft.com> wrote in message
news:8oadnQrloLlHarndRVn-sA@magma.ca...
> Here is an example of how to use "clock enables".
>
> The example uses one of the count states as the "emable"
> Variable a will be updated every 4th 4Mhz clock (at a 1Mhz
> interval).
>
> always @ (posedge 4Mhz)
> begin
>   cnt[1:0] <= cnt[1:0] + 1;
>
>   if (cnt == 3) a <= b;
>  else a <= b;
> end
>
> "Geir Botterli" <geirb@fokk.org> wrote in message
> news:16o920li0tfoia1qq0hpm4bbl9sj6krha1@4ax.com...
> > "John_H" <johnhandwork@mail.com> wrote in message
> > <dcyUb.24$uo1.18709@news-west.eli.net> :
> >
> > Hi, John, thanks for your reply.
> >
> > >Use a single clock for the FPGA.
> > >Use enables to clock the 4 MHz flops and/or the 1 MHz flops at every
nth
> (or
> > >4*n-th) edge.
> >
> > I'm afraid I don't get how I should use clock enables to achieve this.
> > The only "solution" i have come up with is like this:
> >
> > always @ (posedge clk_4MHz)
> >   clk_2MHz <= ~clk_2MHz;
> >
> > always @ (posedge clk_2MHz)
> >   clk_1MHz <= ~clk_1MHz;
> >
> > +BUFGs
> >
> > But this will result in a skew between the edges of the 4 and 1 MHz
> > clocks.
> >
> > I could run the 4 MHz clock through some logic to delay it, but I
> > don't like that option very much.
> >
> > Could you give an example on how to do this with clock enables?
> >
> > >One simple clock.
> > >No DLL.
> > >All flops synchronous with no skew.
> > >Apply the multi-cycle constraint through the enables to get your timing
> at 4
> > >MHz or 1 MHz.
> > >A thing of beauty.
> >
> > Sounds wonderful :)
> >
> > Regards,
> > -Geir Botterli
> >
> >
>
>

"Mike Lewis" <someone@microsoft.com> wrote in message
<LZWdndi5gp-qYrnd4p2dnA@magma.ca> :

>damn typo ... that should be "else a <= a"
>
>"Mike Lewis" <someone@microsoft.com> wrote in message
>news:8oadnQrloLlHarndRVn-sA@magma.ca...
>> Here is an example of how to use "clock enables".
>>
>> The example uses one of the count states as the "emable"
>> Variable a will be updated every 4th 4Mhz clock (at a 1Mhz
>> interval).
>>
>> always @ (posedge 4Mhz)
>> begin
>>   cnt[1:0] <= cnt[1:0] + 1;
>>
>>   if (cnt == 3) a <= b;
>>  else a <= b;
>> end

Thanks, but wouldn't this approach also create a couple of gate delays
worth of skew between the clocks?

-Geir

On Sat, 07 Feb 2004 09:36:09 -0500, Mike Lewis wrote:

> Here is an example of how to use "clock enables".
> 
> The example uses one of the count states as the "emable"
> Variable a will be updated every 4th 4Mhz clock (at a 1Mhz
> interval).
> 
> always @ (posedge 4Mhz)
> begin
>   cnt[1:0] <= cnt[1:0] + 1;
> 
>   if (cnt == 3) a <= b;
>  else a <= b;
> end
> 

You don't use an else for clock enables, here is cleaner version of the
above.

reg [1:0] cnt;
reg ce;

always@(posedge 4mhz) begin
 cnt <= cnt + 1;
 ce <= cnt == 2;
 if(ce) begin
	foo <= bar;
 end
end

There isn't any skew problem, the clock is always the 4Mhz clock. The ce
controls a mux which either selects the new value or the current value,
i.e. the above example is equivalent to the previous posters example.
However the way that I wrote it is what synthesizers expect to see. Also
all FPGAs, both Xilnx and Altera incorporate the clock enable logic into
the flip flops so it's effectively free.

As for DLLs, at 1MHz you don't need them. Also you won't have to worry
about multi-cycle clock constraints, just put a constraint on the 4Mhz
clock. 4Mhz is so slow that it's practically impossible to write any code
that can't meet 4Mhz timing.

Re: your title...."Challenges" are for managers and manger wanna-bes
who have been taught that "problem" is a four letter word.  Problems
are solved by engineers.

Does the Virtex E have a DCM?

Anyway, as somebody else pointed out, use enables (which end up in the
combinatorial logic of your D inputs).

if(clk'event and clk='1') then
  if(slow_en='1') then
    q<=d;
  end if;
end if;




Geir Botterli <geirb@fokk.org> wrote in message news:<308520dbkbv5fm4m3h0ap35n21rrgbqn8e@4ax.com>...
> Greetings, this is my first posting to this group, but I've been
> following the discussions for some time.
> 
> I have a small problem which I'm trying to solve:
> 
> My design has a Virtex E, and I need to generate a 1MHz clock and a
> 4MHz clock from a single clock source. The are to be used internally
> and they need to be synchronized. My problem is that the CLKDLLE
> primitive needs a CLKIN of at least 25MHz. I can supply that, I have
> an external oscillator tunable from 0 (or very low at least) to 40MHz.
> But the CLKDLLE can divide by 16 at maximum, thus I cannot use it to
> create the 1MHz clock.
> 
> Do I have any options? Are there any other techniques I may apply to
> perform division and get a minimal clock skew between the two clocks?
> 
> What would happen if I tried to use a CLKIN of 16MHz? No DLL lock?
> 
> Thank you,
> -Geir Botterli

Greetings, Geir.

"Geir Botterli" <geirb@fokk.org> wrote in message
news:16o920li0tfoia1qq0hpm4bbl9sj6krha1@4ax.com...
> "John_H" <johnhandwork@mail.com> wrote in message
> <dcyUb.24$uo1.18709@news-west.eli.net> :
> >Use a single clock for the FPGA.
> >Use enables to clock the 4 MHz flops and/or the 1 MHz flops at every nth
(or
> >4*n-th) edge.
>
> I'm afraid I don't get how I should use clock enables to achieve this.
...
> Could you give an example on how to do this with clock enables?

If you have a 20 MHz clock but you want a 4 MHz counter and a 1 MHz counter,
you need to generate enables that are active every 5th and every 20th master
clocks.  The counters themselves effectively "run" at 20 MHz in this case
but the enables slow that all down.  You then need to look at how to apply
multi-cycle constraints to tell the place & route tools that all registers
fed by "div5" only need a 4MHz cycle time and the "div20" fed registers need
1 MHz timing constraints.  Only the divide signals need to run at 20 MHz.

reg [2:0] div5cnt;
reg [1:0] div20cnt;
reg div5,div20;
always @(posedge Clk20)
  if( div5cnt == 3'h4 )
  begin
    div5cnt <= 3'h0
    div5 <= 1'b1;
    div20cnt <= div20cnt + 2'b1;
    div20 <= (div20cnt == 2'h3);
  end
  else
    div5cnt <= div5cnt + 3'b1;
    div5 <= 1'b0;
//  div20cnt stays the same
    div20 <= 1'b0;
  end

always @(posedge Clk20)
  if( div5 )  Counter4MHz <= Counter4MHz + 1;
always @(posedge Clk20)
  if( div20 )  Counter1MHz <= Counter1MHz + 1;