How to do one hot state machine in verilog for Xilinx V5 using XST

I would like to use one hot state machine in verilog.  I am using
Xilinx V5 FPGA and XST synthesis tool.  May i know the verilog syntex
to do one hot?

Thanks.

CP

<cpandya@yahoo.com> wrote in message 
news:1191538493.180180.182420@w3g2000hsg.googlegroups.com...
>I would like to use one hot state machine in verilog.  I am using
> Xilinx V5 FPGA and XST synthesis tool.  May i know the verilog syntex
> to do one hot?
>
> Thanks.
>
> CP

Repeat 3 times: "Google is gooood."

http://toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/hdlcode15.html 

On Oct 4, 6:12 pm, "John_H" <newsgr...@johnhandwork.com> wrote:
> <cpan...@yahoo.com> wrote in message
>
> news:1191538493.180180.182420@w3g2000hsg.googlegroups.com...
>
> >I would like to use one hot state machine in verilog.  I am using
> > Xilinx V5 FPGA and XST synthesis tool.  May i know the verilog syntex
> > to do one hot?
>
> > Thanks.
>
> > CP
>
> Repeat 3 times: "Google is gooood."
>
> http://toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/hdlcode15.html

I am still unable to see the xst directive that telss the the xst
synthesis tool that the state machine is one-hot.  Is there such a
thing?

Google is good.

On Oct 5, 1:30 am, cpan...@yahoo.com wrote:
> On Oct 4, 6:12 pm, "John_H" <newsgr...@johnhandwork.com> wrote:
>
> > <cpan...@yahoo.com> wrote in message
>
> >news:1191538493.180180.182420@w3g2000hsg.googlegroups.com...
>
> > >I would like to use one hot state machine in verilog.  I am using
> > > Xilinx V5 FPGA and XST synthesis tool.  May i know the verilog syntex
> > > to do one hot?
>
> > > Thanks.
>
> > > CP
>
> > Repeat 3 times: "Google is gooood."
>
> >http://toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/hdlcode15.html
>
> I am still unable to see the xst directive that telss the the xst
> synthesis tool that the state machine is one-hot.  Is there such a
> thing?
>
> Google is good.

Find "XST User Guide" (in PDF) on xilinx.com. You will find plenty of
informations about XST. The same goes for "Constraints Guide" (also
PDF).

>From the doc:
(for VHDL)
attribute fsm_encoding of {entity_name|signal_name}: {entity|signal}
is
"{auto|one-hot|compact|gray|sequential|johnson|speed1|user}";
(for Verilog)
// synthesis attribute fsm_encoding [of] {module_name|signal_name}
[is] {auto|one-hot|compact|gray|sequential|johnson|speed1|user};

Cheers

I do believe the xilinx tools default to 1-hot implementation if left 
unspecified.

On Oct 5, 12:38 am, Jeff Cunningham <j...@sover.net> wrote:
> I do believe the xilinx tools default to 1-hot implementation if left
> unspecified.


This is in fact true.  It's also very annoying if you don't realize
this and scratch your head for days wondering why a simple state
machine with a 3-bit binary encoding and 8 states can lock up...