vhdl code LED1 <= some_signal; LED2 <= blink_one_second; the LED1,2 are connected to LED's blink_one_second is simple wire that drives LED2 and nothing else. now the code works in real FPGA with following behaviour: when some_signal = 0, then LED2 blinks. when some_signal = 1, then both LEDs blink as full sync to each other. what can cause this? some wrong answers: faulty FPGA fabric, bad PCB, bad power supply. eh, the solution to the problem was weird. but it does exist. sure I assumed FPGA fabric faulty first as I had overstressed the FPGA with 5V supply, and reversed 3.3V supply too. but FPGA is alive and fully working, yet the weird behaviour exist. and this is actually correct behaviour in the particular case. I wonder if somebody is able to quess the answer to the issue. happy thinking! Antti
FPGA quiz: what can be wrong
Started by ●October 15, 2007
Reply by ●October 15, 20072007-10-15
> > I wonder if somebody is able to quess the answer to the issue. happy > thinking! > > Antti >incorrect ucf file had some other signals driving the pins? LEDs are installed backwards and there is also maybe a short?
Reply by ●October 15, 20072007-10-15
On 15 Okt., 17:59, Jeff Cunningham <j...@sover.net> wrote:> > I wonder if somebody is able to quess the answer to the issue. happy > > thinking! > > > Antti > > incorrect ucf file had some other signals driving the pins? > > LEDs are installed backwards and there is also maybe a short?no. no pin mapping problem, no LED connection problems. if LED1 and LED 2 are driven from other signal they work properly. keep thinking;) I solved the issue, but to avoig going nuts I called my wife to look the code too. then id take some break and slept over it. and finally solved. Antti
Reply by ●October 15, 20072007-10-15
Bad Power Supply? Ground loop or supply instability generating continuous powerup of you FPGA. Bad VHDL coding? Description of asynchronous logic (latches). Laurent Antti wrote:> vhdl code > > LED1 <= some_signal; > LED2 <= blink_one_second; > > the LED1,2 are connected to LED's > blink_one_second is simple wire that drives LED2 and nothing else. > > now the code works in real FPGA with following behaviour: > > when some_signal = 0, then LED2 blinks. > when some_signal = 1, then both LEDs blink as full sync to each other. > > what can cause this? > > some wrong answers: faulty FPGA fabric, bad PCB, bad power supply. > > eh, the solution to the problem was weird. but it does exist. sure I > assumed FPGA fabric faulty first as I had overstressed the FPGA with > 5V supply, and reversed 3.3V supply too. but FPGA is alive and fully > working, yet the weird behaviour exist. and this is actually correct > behaviour in the particular case. > > I wonder if somebody is able to quess the answer to the issue. happy > thinking! > > Antti >
Reply by ●October 15, 20072007-10-15
On 15 Okt., 19:38, "Amontec, Larry" <laurent.ga...@ANTI- SPAMamontec.com> wrote:> Bad Power Supply? > Ground loop or supply instability generating continuous powerup of you FPGA. > > Bad VHDL coding? > Description of asynchronous logic (latches). > > LaurentNO NO NO NO waiting for more suggestions :) Antti
Reply by ●October 15, 20072007-10-15
Antti wrote:> On 15 Okt., 19:38, "Amontec, Larry" <laurent.ga...@ANTI- > SPAMamontec.com> wrote: > >>Bad Power Supply? >>Ground loop or supply instability generating continuous powerup of you FPGA. >> >>Bad VHDL coding? >>Description of asynchronous logic (latches). >> >>Laurent > > > NO > NO > NO > NO > > waiting for more suggestions :) > > Antti >if this is not the VHDL code, let us know the VHDL generating the some_signal and the blink_one_second.
Reply by ●October 15, 20072007-10-15
On 15 Okt., 19:58, "Amontec, Larry" <laurent.ga...@ANTI- SPAMamontec.com> wrote:> Antti wrote: > > On 15 Okt., 19:38, "Amontec, Larry" <laurent.ga...@ANTI- > > SPAMamontec.com> wrote: > > >>Bad Power Supply? > >>Ground loop or supply instability generating continuous powerup of you FPGA. > > >>Bad VHDL coding? > >>Description of asynchronous logic (latches). > > >>Laurent > > > NO > > NO > > NO > > NO > > > waiting for more suggestions :) > > > Antti > > if this is not the VHDL code, let us know the VHDL generating the > some_signal and the blink_one_second.- Zitierten Text ausblenden - > > - Zitierten Text anzeigen -the signal driving LED2 goes only to LED2, also no signals used to generate blink_one_second are in any way used in the part that generates some_signal, let say some_signal comes from external switch directly, and has no FPGA logic except routing. Antti
Reply by ●October 15, 20072007-10-15
I had a somewhat similar puzzle quite a few years ago. The code had a flip-flop generating out1 and an async assignment out2 = not out1. The two outputs were driving external buffers. Somehow the outputs got enabled together and the buffers smoked. I traced the problem to the synthesizer setting, which created another flop for the out2 and moved negation to its input. I don't remember all the details now, but IIRC the clock was missing for whatever reason when I first powered the board... Apparently debugging that board was my first assignment at a new job. Imagine how I felt when it smoked :) /Mikhail
Reply by ●October 15, 20072007-10-15
On 15 Okt., 20:26, "MM" <mb...@yahoo.com> wrote:> I had a somewhat similar puzzle quite a few years ago. The code had a > flip-flop generating out1 and an async assignment out2 = not out1. The two > outputs were driving external buffers. Somehow the outputs got enabled > together and the buffers smoked. I traced the problem to the synthesizer > setting, which created another flop for the out2 and moved negation to its > input. I don't remember all the details now, but IIRC the clock was missing > for whatever reason when I first powered the board... Apparently debugging > that board was my first assignment at a new job. Imagine how I felt when it > smoked :) > > /Mikhaileh, but no one is getting closer to my issue. another hint, no flip flip or any sync logic thing is causing this problem. its also not in any way some compiler or P&R weirdness at all. Antti
Reply by ●October 15, 20072007-10-15
On Oct 15, 11:33 am, Antti <Antti.Luk...@googlemail.com> wrote:> On 15 Okt., 20:26, "MM" <mb...@yahoo.com> wrote: > eh, but no one is getting closer to my issue. > another hint, no flip flip or any sync logic thing is causing this > problem. > its also not in any way some compiler or P&R weirdness at all. > > AnttiDid someone get too cheap in the board design and only use a single current limit resistor for both LEDs? If the blink LED has a significantly lower forward drop than the some_signal LED, then when blink LED turns on, it turns off some_signal LED, and when it goes off, some_signal LED comes back on. (You said they blink at the same time, but didn't mention polarity).





