FPGA quiz: what can be wrong

On 15 Okt., 22:22, JustJohn <john.l.sm...@l-3com.com> wrote:
> On Oct 15, 11:33 am, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > On 15 Okt., 20:26, "MM" <mb...@yahoo.com> wrote:
> > eh, but no one is getting closer to my issue.
> > another hint, no flip flip or any sync logic thing is causing this
> > problem.
> > its also not in any way some compiler or P&R weirdness at all.
>
> > Antti
>
> Did someone get too cheap in the board design and only use a single
> current limit resistor for both LEDs? If the blink LED has a
> significantly lower forward drop than the some_signal LED, then when
> blink LED turns on, it turns off some_signal LED, and when it goes
> off, some_signal LED comes back on. (You said they blink at the same
> time, but didn't mention polarity).

same blink rate, same polarity.
but it was a good guess.
and no it has nothing todo with the LED external wiring.

Antti

>> incorrect ucf file had some other signals driving the pins?
>>
>> LEDs are installed backwards and there is also maybe a short?
> 
> no.
> no pin mapping problem, no LED connection problems.
> if LED1 and LED 2 are driven from other signal they work properly.
> keep thinking;)

Are the IO bank VCCO's, IO types and LED drive levels properly matched up?

Elsewhere in your code, is some_signal or blink_one_second ever assigned 
the value 'Z'?

"Antti" <Antti.Lukats@googlemail.com> wrote in message 
news:1192462938.206319.120810@i13g2000prf.googlegroups.com...
>
> vhdl code
>
> LED1 <= some_signal;
> LED2 <= blink_one_second;
>
> the LED1,2 are connected to LED's
> blink_one_second is simple wire that drives LED2 and nothing else.
>
> now the code works in real FPGA with following behaviour:
>
> when some_signal = 0, then LED2 blinks.
> when some_signal = 1, then both LEDs blink as full sync to each other.
>
> what can cause this?
>
Hi Antti,
Later on in your code you wrote:-

LED1 <= blink_one_second AND some_signal;

Do I win &#4294967295;5?
Cheers, Syms. 

Antti wrote:
> vhdl code
> 
> LED1 <= some_signal;
> LED2 <= blink_one_second;
> 
> the LED1,2 are connected to LED's
> blink_one_second is simple wire that drives LED2 and nothing else.
> 
> now the code works in real FPGA with following behaviour:
> 
> when some_signal = 0, then LED2 blinks.
> when some_signal = 1, then both LEDs blink as full sync to each other.
> 
> what can cause this?
> 
> some wrong answers: faulty FPGA fabric, bad PCB, bad power supply.
> 
> eh, the solution to the problem was weird. but it does exist. sure I
> assumed FPGA fabric faulty first as I had overstressed the FPGA with
> 5V supply, and reversed 3.3V supply too. but FPGA is alive and fully
> working, yet the weird behaviour exist. and this is actually correct
> behaviour in the particular case.
> 
> I wonder if somebody is able to quess the answer to the issue. happy
> thinking!
> 
> Antti
> 

One of the LEDs was installed backwards?

"Antti" <Antti.Lukats@googlemail.com> wrote in message 
news:1192473204.719381.50050@t8g2000prg.googlegroups.com...
>
> eh, but no one is getting closer to my issue.
> another hint, no flip flip or any sync logic thing is causing this
> problem.
> its also not in any way some compiler or P&R weirdness at all.
>

I think you should explain how the LEDs are connected. I don't think what 
you are describing would be possible if the LEDs were connected through 
individual current-limiting resistors with their anodes to FPGA pins and 
with their cathodes to GND. Also, I assume no FPGA special-purpose pins are 
involved...

/Mikhail 

Antti wrote:
(...)
> 
> I wonder if somebody is able to quess the answer to the issue. happy
> thinking!
> 
> Antti
> 


Hi Antti

I would suggest an incorrect mapping between the physical pins and the 
VHDL top-level ports (bad or missing UCF file).

Antti wrote:
> On 15 Okt., 20:26, "MM" <mb...@yahoo.com> wrote:
> 
>>I had a somewhat similar puzzle quite a few years ago. The code had a
>>flip-flop generating  out1 and an async assignment out2 = not out1. The two
>>outputs were driving external buffers. Somehow the outputs got enabled
>>together and the buffers smoked. I traced the problem to the synthesizer
>>setting, which created another flop for the out2 and moved negation to its
>>input. I don't remember all the details now, but IIRC the clock was missing
>>for whatever reason when I first powered the board... Apparently debugging
>>that board was my first assignment at a new job. Imagine how I felt when it
>>smoked :)
>>
>>/Mikhail
> 
> 
> eh, but no one is getting closer to my issue.
> another hint, no flip flip or any sync logic thing is causing this
> problem.
> its also not in any way some compiler or P&R weirdness at all.

  Candidates are
* Post-Pin error - Verifiable by checking the PIN levels, and 
dual-mapping the outputs.
* Config/Mapping error (eg terminator enabled by accident, really slow 
clock etc )
* Logic Error. If the FPGA is OK, and the Compile/P&R is also OK
   that leaves the classic 'Cockpit error'

-jg

Antti wrote:

> 
> vhdl code
> 
> LED1 <= some_signal;
> LED2 <= blink_one_second;
> 
> the LED1,2 are connected to LED's
> blink_one_second is simple wire that drives LED2 and nothing else.
> 
> now the code works in real FPGA with following behaviour:
> 
> when some_signal = 0, then LED2 blinks. when some_signal = 1, then both
> LEDs blink as full sync to each other.
> 
> what can cause this?

DCI.


-- 
Phil Hays

weak/no internal pull-up/down on LED1? Drive current?

On 16 Okt., 04:04, Matthieu <m.a.t.t.h.i.e.u.m.i.c.h....@laposte.net>
wrote:
> Antti wrote:
>
> (...)
>
>
>
> > I wonder if somebody is able to quess the answer to the issue. happy
> > thinking!
>
> > Antti
>
> Hi Antti
>
> I would suggest an incorrect mapping between the physical pins and the
> VHDL top-level ports (bad or missing UCF file).

no