VHDL trivia?

Hi folks!

A bit of VHDL trivia.

What I want is the reverse of:


one_hot_gen: for i in 0 to 15 generate
begin
    one_hot(i) <= '1' when CONV_INTEGER(address) = i else '0';
end generate;


the only idea I had contains 'Z's, which the tools will swallow and
convert to logic - it works, but there _has_ to be a nicer way?


address <= "0000" when one_hot(0) = '1' else "ZZZZ";
address_gen: for i in 1 to 15 generate
begin
    address2 <= CONV_STD_LOGIC_VECTOR(CONV_UNSIGNED(i, 4), 4)
                when one_hot(i) = '1'
                and CONV_INTEGER(one_hot(i - 1 downto 0)) = 0
                else "ZZZZ";
end generate;


Any ideas?

-   Philip
-- 
Democracy: Three wolves and a sheep voting on what's
for dinner.

how about a big case statement ?

case OneHot is
when X"0001" => Address <=  X"0";
when X"0002" => Address <=  X"1";
when X"0004" => Address <=  X"2";
when X"0008" => Address <=  X"3";
when X"0010" => Address <=  X"4";
when X"0020" => Address <=  X"5";
when X"0040" => Address <=  X"6";
when X"0080" => Address <=  X"7";
when X"0100" => Address <=  X"8";
when X"0200" => Address <=  X"9";
when X"0400" => Address <=  X"A";
when X"0800" => Address <=  X"B";
when X"1000" => Address <=  X"C";
when X"2000" => Address <=  X"D";
when X"4000" => Address <=  X"E";
when others => Address <=  X"F";
end case;

jan.kindt wrote:
> how about a big case statement ?

Gets too big if the width grows, and doesn't work with generic widths... :(

-   Philip
-- 
Democracy: Three wolves and a sheep voting on what's
for dinner.

"Philip Herzog" <phq@arcor.de> wrote in message 
news:471768C4.90800@arcor.de...
> jan.kindt wrote:
>> how about a big case statement ?
>
> Gets too big if the width grows, and doesn't work with generic widths... 
> :(
>
> -   Philip
>
Hi Philip,
Perhaps comp.lang.vhdl might be a better place to ask?
HTH., Syms. 

On Oct 18, 10:08 am, Philip Herzog <p...@arcor.de> wrote:
> jan.kindt wrote:
> > how about a big case statement ?
>
> Gets too big if the width grows, and doesn't work with generic widths... :(
>
> -   Philip
> --
> Democracy: Three wolves and a sheep voting on what's
> for dinner.

What about:

process(one_hot)
variable temp : integer range 0 to 15;
begin
   for k in one_hot'range loop
      if one_hot(k) = '1' then
         temp <= k;
      end if;
   end loop;
   address <= to_unsigned(temp, 16);
end process;

Although I think the case statement approach probably synthesizes a
lot nicer, and is much nicer code. I'm pretty sure this will
synthesize, but I'd build a test module with small vectors first and
check the RTL viewer to make sure it turns into something that makes
sense.

>
> Although I think the case statement approach probably synthesizes a
> lot nicer, and is much nicer code. I'm pretty sure this will
> synthesize, but I'd build a test module with small vectors first and
> check the RTL viewer to make sure it turns into something that makes
> sense.

Hi,

Shown below is a HDFS binary to onehot convertor which can generate
VHDL or Verilog designs for any width input.

The first one generates a case statement - it's the one I would use if
I were writing the code in VHDL and I'd assume it would produce the
best implementation.  The second one generates a structural
implementation using multiplexors and or gates.  I wouldn't even
consider writing this by hand.  However, for a 16 bit onehot input,
the case statement version requires 39 luts, while the structural
version needs just 12 luts.  The difference lies in how the two
versions deal with invalid inputs, though I was very surprised at just
how big that difference was.

Cheers,

Andy
http://code.google.com/p/hdfs/

compile:
> fsc -r hdfs.dll -r hdfslib.dll b21h.ml

case statement version, 56 bit one hot input vector, verilog out
> b21h.exe behave verilog 56

structural version, 16 bit one hot input vector, vhdl out
> b21h.exe struct vhdl 16

(* binary to one hot circuit, VHDL/Verilog generator and simulator *)

#light
open DigitalLogic
open Numeric.Ops
open Signal

(* convert one hot vector to binary.  Behavioural implementation using
a case statement.
   If the one hot vector is invalid  (zero or more than one bit is
set) then the output is set to zero *)
let onehot_to_binary_b onehot =
  let owidth = width onehot
  let bwidth = Util.clog2 (owidth-1)
  let binary = b_wire0 bwidth
  let match_case n m = [ for i in 0 .. n-1 -> if (n-i-1)=m then "1"
else "0" ] |> String.concat ""
  behave
    [
      b_switch onehot
        [ for i in { 0 .. owidth-1 } -> b_case (constb (match_case
owidth i)) [ binary $== consti bwidth i ] ]
    ];
  binary.q

(* convert one hot vector to binary.  Structural implementation using
multiplexors.
   Behaviour is undefined if the one hot vector is invalid - at a
rough guess, 0 in 0 out, otherwise
   the highest set bit is chosen *)
let onehot_to_binary_s onehot =
  let owidth = width onehot in
  let bwidth = Util.clog2 (owidth-1) in
  let rec split_and_mux onehot value =
    match width onehot with
    | 1 -> consti bwidth value, onehot
    | n when n>0 ->
      let hi,lo = split onehot
      let (hi,hictrl),(lo,loctrl) = split_and_mux hi (value + width
lo), split_and_mux lo value
      hictrl.mux2(hi, lo), (hictrl ||| loctrl)
    | _ -> failwith "split_and_mux error"
  fst (split_and_mux onehot 0)

let argv =
#if INTERACTIVE
  fsi.CommandLineArgs
#else
  Sys.argv
#endif

let gen_onehot_to_binary core_type hdl onehot_bits =
  (* build circuit *)
  let onehot = input "onehot" onehot_bits
  let onehot_to_binary =
    match core_type with
    | "behave" -> onehot_to_binary_b
    | "struct" -> onehot_to_binary_s
    | _ -> failwith "Invalid core type"
  let write,ext =
    match hdl with
    | "vhdl" -> Vhdl.write, ".vhd"
    | "verilog" -> Verilog.write, ".v"
    | _ -> failwith "Invalid hdl type"
  let circuit = [ (onehot_to_binary onehot).output "binary" ] |>
Circuit.create
  (* write hdl *)
  Circuit.write_file write "" ("onehot_to_binary_" ^ core_type ^ "_" ^
string_of_int onehot_bits) ext circuit
  (* simulate *)
  let sim,data = (Simulator.create circuit).record
  sim.reset
  let binary n m = [ for i in 0 .. n-1 -> if (n-i-1)=m then "1" else
"0" ] |> String.concat ""
  for i=0 to onehot_bits-1 do
    sim.[onehot].b <- binary onehot_bits i
    sim.cycle
  Waveform.draw2 data Waveform.HexFormat

do gen_onehot_to_binary argv.(1) argv.(2) (int_of_string argv.(3))

********************************* example output

--------------------------------------------------------
-- Generated by HDFS version 0.2.1
-- http://code.google.com/p/hdfs/
--------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity onehot_to_binary_behave_16 is
port (
 onehot : in std_logic_vector(15 downto 0);
 binary : out std_logic_vector(3 downto 0));
end;

architecture hdfs of onehot_to_binary_behave_16 is
 -- .....some stuff cut out here

 -- declarations
 constant  hdfs_135 :  std_logic_vector(3 downto 0) := "1111";
 constant  hdfs_133 :  std_logic_vector(3 downto 0) := "1110";
 constant  hdfs_131 :  std_logic_vector(3 downto 0) := "1101";
 constant  hdfs_129 :  std_logic_vector(3 downto 0) := "1100";
 constant  hdfs_127 :  std_logic_vector(3 downto 0) := "1011";
 constant  hdfs_125 :  std_logic_vector(3 downto 0) := "1010";
 constant  hdfs_123 :  std_logic_vector(3 downto 0) := "1001";
 constant  hdfs_121 :  std_logic_vector(3 downto 0) := "1000";
 constant  hdfs_119 :  std_logic_vector(3 downto 0) := "0111";
 constant  hdfs_117 :  std_logic_vector(3 downto 0) := "0110";
 constant  hdfs_115 :  std_logic_vector(3 downto 0) := "0101";
 constant  hdfs_113 :  std_logic_vector(3 downto 0) := "0100";
 constant  hdfs_111 :  std_logic_vector(3 downto 0) := "0011";
 constant  hdfs_109 :  std_logic_vector(3 downto 0) := "0010";
 constant  hdfs_107 :  std_logic_vector(3 downto 0) := "0001";
 constant  hdfs_105 :  std_logic_vector(3 downto 0) := "0000";
 constant  hdfs_102 :  std_logic_vector(3 downto 0) := "0000";
 signal  hdfs_103 :  std_logic_vector(3 downto 0);
 signal  hdfs_136 :  std_logic_vector(3 downto 0);

begin

 -- logic
 process ( onehot ) is begin
  hdfs_136 <= hdfs_102;
  case onehot is
   when "0000000000000001" =>
    hdfs_136 <= hdfs_105;
   when "0000000000000010" =>
    hdfs_136 <= hdfs_107;
   when "0000000000000100" =>
    hdfs_136 <= hdfs_109;
   when "0000000000001000" =>
    hdfs_136 <= hdfs_111;
   when "0000000000010000" =>
    hdfs_136 <= hdfs_113;
   when "0000000000100000" =>
    hdfs_136 <= hdfs_115;
   when "0000000001000000" =>
    hdfs_136 <= hdfs_117;
   when "0000000010000000" =>
    hdfs_136 <= hdfs_119;
   when "0000000100000000" =>
    hdfs_136 <= hdfs_121;
   when "0000001000000000" =>
    hdfs_136 <= hdfs_123;
   when "0000010000000000" =>
    hdfs_136 <= hdfs_125;
   when "0000100000000000" =>
    hdfs_136 <= hdfs_127;
   when "0001000000000000" =>
    hdfs_136 <= hdfs_129;
   when "0010000000000000" =>
    hdfs_136 <= hdfs_131;
   when "0100000000000000" =>
    hdfs_136 <= hdfs_133;
   when "1000000000000000" =>
    hdfs_136 <= hdfs_135;
   when others => null;
  end case;
 end process;

 hdfs_103 <= hdfs_136;

 binary <= hdfs_103;

end architecture;

--------------------------------------------------------
-- Generated by HDFS version 0.2.1
-- http://code.google.com/p/hdfs/
--------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity onehot_to_binary_struct_16 is
port (
 onehot : in std_logic_vector(15 downto 0);
 binary : out std_logic_vector(3 downto 0));
end;

architecture hdfs of onehot_to_binary_struct_16 is

 -- declarations
 constant  hdfs_110 :  std_logic_vector(3 downto 0) := "1111";
 constant  hdfs_111 :  std_logic_vector(3 downto 0) := "1110";
 constant  hdfs_116 :  std_logic_vector(3 downto 0) := "1101";
 constant  hdfs_117 :  std_logic_vector(3 downto 0) := "1100";
 constant  hdfs_126 :  std_logic_vector(3 downto 0) := "1011";
 constant  hdfs_127 :  std_logic_vector(3 downto 0) := "1010";
 constant  hdfs_132 :  std_logic_vector(3 downto 0) := "1001";
 constant  hdfs_133 :  std_logic_vector(3 downto 0) := "1000";
 constant  hdfs_146 :  std_logic_vector(3 downto 0) := "0111";
 constant  hdfs_147 :  std_logic_vector(3 downto 0) := "0110";
 constant  hdfs_152 :  std_logic_vector(3 downto 0) := "0101";
 constant  hdfs_153 :  std_logic_vector(3 downto 0) := "0100";
 constant  hdfs_162 :  std_logic_vector(3 downto 0) := "0011";
 constant  hdfs_163 :  std_logic_vector(3 downto 0) := "0010";
 constant  hdfs_168 :  std_logic_vector(3 downto 0) := "0001";
 constant  hdfs_169 :  std_logic_vector(3 downto 0) := "0000";
 signal  hdfs_112 :  std_logic_vector(3 downto 0);
 signal  hdfs_118 :  std_logic_vector(3 downto 0);
 signal  hdfs_120 :  std_logic_vector(3 downto 0);
 signal  hdfs_128 :  std_logic_vector(3 downto 0);
 signal  hdfs_134 :  std_logic_vector(3 downto 0);
 signal  hdfs_136 :  std_logic_vector(3 downto 0);
 signal  hdfs_138 :  std_logic_vector(3 downto 0);
 signal  hdfs_148 :  std_logic_vector(3 downto 0);
 signal  hdfs_154 :  std_logic_vector(3 downto 0);
 signal  hdfs_156 :  std_logic_vector(3 downto 0);
 signal  hdfs_164 :  std_logic_vector(3 downto 0);
 signal  hdfs_159 :  std_logic_vector(1 downto 0);
 signal  hdfs_166 :  std_logic;
 signal  hdfs_170 :  std_logic_vector(3 downto 0);
 signal  hdfs_161 :  std_logic;
 signal  hdfs_141 :  std_logic_vector(3 downto 0);
 signal  hdfs_158 :  std_logic_vector(1 downto 0);
 signal  hdfs_160 :  std_logic;
 signal  hdfs_165 :  std_logic;
 signal  hdfs_172 :  std_logic_vector(3 downto 0);
 signal  hdfs_151 :  std_logic;
 signal  hdfs_143 :  std_logic_vector(1 downto 0);
 signal  hdfs_150 :  std_logic;
 signal  hdfs_155 :  std_logic;
 signal  hdfs_145 :  std_logic;
 signal  hdfs_103 :  std_logic_vector(7 downto 0);
 signal  hdfs_140 :  std_logic_vector(3 downto 0);
 signal  hdfs_142 :  std_logic_vector(1 downto 0);
 signal  hdfs_144 :  std_logic;
 signal  hdfs_149 :  std_logic;
 signal  hdfs_157 :  std_logic;
 signal  hdfs_174 :  std_logic_vector(3 downto 0);
 signal  hdfs_131 :  std_logic;
 signal  hdfs_123 :  std_logic_vector(1 downto 0);
 signal  hdfs_130 :  std_logic;
 signal  hdfs_135 :  std_logic;
 signal  hdfs_125 :  std_logic;
 signal  hdfs_105 :  std_logic_vector(3 downto 0);
 signal  hdfs_122 :  std_logic_vector(1 downto 0);
 signal  hdfs_124 :  std_logic;
 signal  hdfs_129 :  std_logic;
 signal  hdfs_137 :  std_logic;
 signal  hdfs_115 :  std_logic;
 signal  hdfs_107 :  std_logic_vector(1 downto 0);
 signal  hdfs_114 :  std_logic;
 signal  hdfs_119 :  std_logic;
 signal  hdfs_109 :  std_logic;
 signal  hdfs_102 :  std_logic_vector(7 downto 0);
 signal  hdfs_104 :  std_logic_vector(3 downto 0);
 signal  hdfs_106 :  std_logic_vector(1 downto 0);
 signal  hdfs_108 :  std_logic;
 signal  hdfs_113 :  std_logic;
 signal  hdfs_121 :  std_logic;
 signal  hdfs_139 :  std_logic;
 signal  hdfs_176 :  std_logic_vector(3 downto 0);

begin

 -- logic
 hdfs_112 <= hdfs_111 when hdfs_108 = '0' else hdfs_110;
 hdfs_118 <= hdfs_117 when hdfs_114 = '0' else hdfs_116;
 hdfs_120 <= hdfs_118 when hdfs_113 = '0' else hdfs_112;
 hdfs_128 <= hdfs_127 when hdfs_124 = '0' else hdfs_126;
 hdfs_134 <= hdfs_133 when hdfs_130 = '0' else hdfs_132;
 hdfs_136 <= hdfs_134 when hdfs_129 = '0' else hdfs_128;
 hdfs_138 <= hdfs_136 when hdfs_121 = '0' else hdfs_120;
 hdfs_148 <= hdfs_147 when hdfs_144 = '0' else hdfs_146;
 hdfs_154 <= hdfs_153 when hdfs_150 = '0' else hdfs_152;
 hdfs_156 <= hdfs_154 when hdfs_149 = '0' else hdfs_148;
 hdfs_164 <= hdfs_163 when hdfs_160 = '0' else hdfs_162;
 hdfs_159 <= hdfs_141(1 downto 0);
 hdfs_166 <= hdfs_159(1);
 hdfs_170 <= hdfs_169 when hdfs_166 = '0' else hdfs_168;
 hdfs_161 <= hdfs_158(0);
 hdfs_141 <= hdfs_103(3 downto 0);
 hdfs_158 <= hdfs_141(3 downto 2);
 hdfs_160 <= hdfs_158(1);
 hdfs_165 <= hdfs_sl( hdfs_uns(hdfs_160) or hdfs_uns(hdfs_161) );
 hdfs_172 <= hdfs_170 when hdfs_165 = '0' else hdfs_164;
 hdfs_151 <= hdfs_143(0);
 hdfs_143 <= hdfs_140(1 downto 0);
 hdfs_150 <= hdfs_143(1);
 hdfs_155 <= hdfs_sl( hdfs_uns(hdfs_150) or hdfs_uns(hdfs_151) );
 hdfs_145 <= hdfs_142(0);
 hdfs_103 <= onehot(7 downto 0);
 hdfs_140 <= hdfs_103(7 downto 4);
 hdfs_142 <= hdfs_140(3 downto 2);
 hdfs_144 <= hdfs_142(1);
 hdfs_149 <= hdfs_sl( hdfs_uns(hdfs_144) or hdfs_uns(hdfs_145) );
 hdfs_157 <= hdfs_sl( hdfs_uns(hdfs_149) or hdfs_uns(hdfs_155) );
 hdfs_174 <= hdfs_172 when hdfs_157 = '0' else hdfs_156;
 hdfs_131 <= hdfs_123(0);
 hdfs_123 <= hdfs_105(1 downto 0);
 hdfs_130 <= hdfs_123(1);
 hdfs_135 <= hdfs_sl( hdfs_uns(hdfs_130) or hdfs_uns(hdfs_131) );
 hdfs_125 <= hdfs_122(0);
 hdfs_105 <= hdfs_102(3 downto 0);
 hdfs_122 <= hdfs_105(3 downto 2);
 hdfs_124 <= hdfs_122(1);
 hdfs_129 <= hdfs_sl( hdfs_uns(hdfs_124) or hdfs_uns(hdfs_125) );
 hdfs_137 <= hdfs_sl( hdfs_uns(hdfs_129) or hdfs_uns(hdfs_135) );
 hdfs_115 <= hdfs_107(0);
 hdfs_107 <= hdfs_104(1 downto 0);
 hdfs_114 <= hdfs_107(1);
 hdfs_119 <= hdfs_sl( hdfs_uns(hdfs_114) or hdfs_uns(hdfs_115) );
 hdfs_109 <= hdfs_106(0);
 hdfs_102 <= onehot(15 downto 8);
 hdfs_104 <= hdfs_102(7 downto 4);
 hdfs_106 <= hdfs_104(3 downto 2);
 hdfs_108 <= hdfs_106(1);
 hdfs_113 <= hdfs_sl( hdfs_uns(hdfs_108) or hdfs_uns(hdfs_109) );
 hdfs_121 <= hdfs_sl( hdfs_uns(hdfs_113) or hdfs_uns(hdfs_119) );
 hdfs_139 <= hdfs_sl( hdfs_uns(hdfs_121) or hdfs_uns(hdfs_137) );
 hdfs_176 <= hdfs_174 when hdfs_139 = '0' else hdfs_138;

 binary <= hdfs_176;

end architecture;

Philip Herzog wrote:
> Hi folks!
> 
> A bit of VHDL trivia.
> 
> What I want is the reverse of:
> 
> 
> one_hot_gen: for i in 0 to 15 generate
> begin
>     one_hot(i) <= '1' when CONV_INTEGER(address) = i else '0';
> end generate;

How about

    addr_p: process (one_hot)
    begin
       address <= (others => '0');
       for i in 1 to 15 loop
          if one_hot(i) = '1' then
             address <= to_unsigned(i, 4);
          end if;
       end loop;
    end process addr_p;

On Thu, 18 Oct 2007 20:21:25 GMT, 
Duane Clark <junkmail@junkmail.com> wrote:

>> What I want is the reverse of:
>> one_hot_gen: [...]
>
>How about
>
>    addr_p: process (one_hot)
>    begin
>       address <= (others => '0');
>       for i in 1 to 15 loop
>          if one_hot(i) = '1' then
>             address <= to_unsigned(i, 4);
>          end if;
>       end loop;
>    end process addr_p;

That, and Dave's similar suggestion, have the
feature (drawback? benefit?) that each lower-priority
bit must check that all higher-priority bits are zero
before asserting its value on to the output.  This is
typically rather extravagant, and it's unnecessary if
you are confident that the one-hot code is indeed one-hot
(or, more likely, you don't care what happens if it isn't).

This form will give you much more compact hardware (just
a few OR gates) at the expense of being somewhat less 
clear.  And if there is more than one bit of the input
"one-hot" code set, it will generate a silly result.

  onehot_to_binary: process (onehot) is
    variable OH: std_logic_vector (one_hot'length-1 downto 0);
    variable result: unsigned(address'range);
  begin
    -- Paranoia: Normalize the onehot vector
    -- so that you don't care how the original
    -- was defined.  Leftmost bit is number N-1,
    -- rightmost bit is number 0.
    OH := onehot;
    -- start the OR-tree
    result := (others => '0');
    -- build the OR-tree
    for i in OH'range loop
      if OH(i) = '1' then
        result := result OR to_unsigned(i, result'length);
      end if;
    end loop;
    -- copy result to your output signal
    address <= result;
  end process;

Tada! optimally small hardware.

No, I don't like it either.  I like it better than 
obscure code-generator scripts, though :-)

By the way: something like
  assert (2 ** address'length) > onehot'length
    report "Address not big enough to fit onehot value"
    severity failure;
sounds good to me.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

On Thu, 18 Oct 2007 15:04:24 +0200, 
Philip Herzog <phq@arcor.de> wrote:

>What I want is the reverse of:
>
>one_hot_gen: for i in 0 to 15 generate
>begin
>    one_hot(i) <= '1' when CONV_INTEGER(address) = i else '0';
>end generate;

See my response to Duane Clark, later in the thread, for a 
direct answer.

HOWEVER... two fairly serious nitpicks with your decoder
design.

1) Break the bad habit of using nasty obsolete flaky 
arithmetic packages, and switch to NUMERIC_STD.  Then
your CONV_INTEGER function (to integer? from integer)
becomes TO_INTEGER, and correctly requires "address"
to be UNSIGNED.

2) The generate loop is unnecessarily obscure, and will
simulate more slowly than is necessary.  Instead, consider
a procedural loop:

  -- assumes Address is declared "unsigned"
  process (address)
  begin
    one_hot <= (others => '0');
    for i in one_hot'range loop
      if address = i then
        one_hot(i) <= '1';
      end if;
    end loop;
  end process;

(Note that it's OK to compare an UNSIGNED address with an
integer, without conversions.)

Or, even better:

  process(address)
  begin
    one_hot <= (others => '0');
    one_hot(to_integer(address)) <= '1';
  end process;
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

"Philip Herzog" <phq@arcor.de> wrote in message 
news:471759D8.1020700@arcor.de...
> Hi folks!
>
> A bit of VHDL trivia.
>
> What I want is the reverse of:
>
>
> one_hot_gen: for i in 0 to 15 generate
> begin
>    one_hot(i) <= '1' when CONV_INTEGER(address) = i else '0';
> end generate;
>
<snip>
> Any ideas?
>

The short answer is shown in the VHDL functions below (for an 8 state one 
hot encoding).  Left as an exercise is extension to other bit widths. 
You'll find that this structure will most likely always result in the 
minimal synthesized logic representation.

function Encode_OneHots(L: std_ulogic_vector) return std_ulogic_vector is
 variable RetVal: std_ulogic_vector(2 downto 0);
begin
 RetVal(0) := L(1) xor L(3) xor L(5) xor L(7);
 RetVal(1) := L(2) xor L(3) xor L(6) xor L(7);
 RetVal(2) := L(4) xor L(5) xor L(6) xor L(7);

 RetVal(0) := L(1) or L(3) or L(5) or L(7);
 RetVal(1) := L(2) or L(3) or L(6) or L(7);
 RetVal(2) := L(4) or L(5) or L(6) or L(7);

 return(RetVal);
end function Encode_OneHots;

function Decode_OneHots(L: std_ulogic_vector) return std_ulogic_vector is
 variable RetVal: std_ulogic_vector(7 downto 0);
begin
 RetVal := (others => '0');
 RetVal(to_integer(unsigned(L))) := '1';
 return(RetVal);

The somewhat longer answer is that darn near every time people talk about 
one-hot encoding it is usually in the context of state machines or 
enumerated types.  In that scenario, one can convert enumerations to/from 
vectors with the functions shown below.  When used in pairs in the correct 
fashion, the pair results in 0 logic gates synthesized.

type My_Type is (s0, s1, s2, s3, s4, s5, s6, s7);

function To_Std_ULogic_Vector(L: My_Type) return std_ulogic_vector is
 variable RetVal: std_ulogic_vector(2 downto 0); -- '2' should be 
log2(My_Type'length) - 1
begin
 RetVal := std_ulogic_vector(to_unsigned(My_Type'pos(L), RetVal'length));
 return(RetVal);
end function To_Std_ULogic_Vector;

function From_Std_ULogic_Vector(L: std_ulogic_vector) return My_Type is
 variable RetVal: My_Type;
begin
 RetVal := My_Type'val(to_integer(unsigned(L)));
 return(RetVal);
end function From_Std_ULogic_Vector;

For an even deeper understanding of the problem about why working directly 
with one hots and reversing the decoding is probably not the best approach 
in the first place, read the side discussion on exactly this topic that 
starts at link below.  That thread will also get into showing why any 
solution that involves if/elsif/end if; or a case statement will result in a 
lot of extra logic being generated (as Andy seems to have rediscovered on 
his last post to your thread).

http://groups.google.com/group/comp.lang.vhdl/browse_frm/thread/77ea136174190b69/0fa19ddd6dbb2fec?lnk=gst&q=orif+KJ#0fa19ddd6dbb2fec

That whole thread is quite long, posts #81-90 cover the gist of what you're 
asking about (the link above is to #81).  90-100 or so go off on another 
tangent and there are even more tangents in there as well.

KJ