Has anyone implemented a circuit similar to the one below?
VCC
+
|
.---------------o
| |
| |
| .-.
| | |
| | | weak pullup
| '-'
| |
| |
| .-----o
| | | -----
| |\| | | |
--------| >-----|-------| PIN |
|/ | | |
| -----
|
| floating
| or
| GND
/| |
To Internal Fpga Logic <---------< |-------
\|
(created by AACircuit v1.28.6 beta 04/19/05 www.tech-chat.de)
When the input pin is floating, the weak pullup causes the output
buffer to drive Vcc out, negating any extraneous noise that may exist
on the external line.
When the input pin is driven to ground, the buffer momentarily tries
driving Vcc to ground but stops once the tristate is disabled.
I've always just used a weak pullup on the input (no tristate buffer
at all) but another engineer in our group says this is a good way to
protect input pins from noise on undriven inputs. I'm a little
concerned about the brief period of time when the tristate buffer is
driving ground but he assures me that the fpga can handle it.
Do you agree?
Another way to handle floating inputs.
Started by ●November 1, 2007
Reply by ●November 1, 20072007-11-01
Reply by ●November 1, 20072007-11-01
Petrov_101@hotmail.com wrote:> Has anyone implemented a circuit similar to the one below? > > VCC > + > | > .---------------o > | | > | | > | .-. > | | | > | | | weak pullup > | '-' > | | > | | > | .-----o > | | | ----- > | |\| | | | > --------| >-----|-------| PIN | > |/ | | | > | ----- > | > | floating > | or > | GND > /| | > To Internal Fpga Logic <---------< |------- > \| > (created by AACircuit v1.28.6 beta 04/19/05 www.tech-chat.de) > > > When the input pin is floating, the weak pullup causes the output > buffer to drive Vcc out, negating any extraneous noise that may exist > on the external line. > > When the input pin is driven to ground, the buffer momentarily tries > driving Vcc to ground but stops once the tristate is disabled. > > I've always just used a weak pullup on the input (no tristate buffer > at all) but another engineer in our group says this is a good way to > protect input pins from noise on undriven inputs.Wow - How much noise is he used to dealing with ?> I'm a little > concerned about the brief period of time when the tristate buffer is > driving ground but he assures me that the fpga can handle it.Also be worried about if the contention can get past the logic threshold.> > Do you agree?Yes, "the fpga can handle it" - but you have wider issues. Can the device driving the fPGA handle it. You would need to spec the lowest drive option on the FPGA, and the best drive on the external device. What if the designer of the external device is thinking exactly the same as you :) The 80C51 has a port structure similar, but they use Weak PFET and Strong NFET, so they know they will not get stuck in no-mans land with part variations. -jg
Reply by ●November 1, 20072007-11-01
On Nov 1, 2:25 pm, austin <aus...@xilinx.com> wrote:> Petrov, > > Why are you trying to do this? > > What is it supposed to protect the FPGA from? > > AustinI'm not convinced I should be trying this, that's the problem. I've always just enabled a weak pullup resistor on the input of a floating pin. My coworker is trying to convince me that this approach offers better noise immunity when nothing is connected to the input pin. The thing is, this input feeds a two-stage synchronizer... I would think that alone would eliminate most noise to the synchronous logic that follows.
Reply by ●November 1, 20072007-11-01
On Nov 1, 2:50 pm, Jim Granville <no.s...@designtools.maps.co.nz> wrote:> Petrov_...@hotmail.com wrote: > > Has anyone implemented a circuit similar to the one below? > > > VCC > > + > > | > > .---------------o > > | | > > | | > > | .-. > > | | | > > | | | weak pullup > > | '-' > > | | > > | | > > | .-----o > > | | | ----- > > | |\| | | | > > --------| >-----|-------| PIN | > > |/ | | | > > | ----- > > | > > | floating > > | or > > | GND > > /| | > > To Internal Fpga Logic <---------< |------- > > \| > > (created by AACircuit v1.28.6 beta 04/19/05www.tech-chat.de) > > > When the input pin is floating, the weak pullup causes the output > > buffer to drive Vcc out, negating any extraneous noise that may exist > > on the external line. > > > When the input pin is driven to ground, the buffer momentarily tries > > driving Vcc to ground but stops once the tristate is disabled. > > > I've always just used a weak pullup on the input (no tristate buffer > > at all) but another engineer in our group says this is a good way to > > protect input pins from noise on undriven inputs. > > Wow - How much noise is he used to dealing with ? > > > I'm a little > > concerned about the brief period of time when the tristate buffer is > > driving ground but he assures me that the fpga can handle it. > > Also be worried about if the contention can get past the logic threshold. > > > > > Do you agree? > > Yes, "the fpga can handle it" - but you have wider issues. > Can the device driving the fPGA handle it. > You would need to spec the lowest drive option on the FPGA, > and the best drive on the external device. > What if the designer of the external device is thinking exactly the same > as you :) > > The 80C51 has a port structure similar, but they use Weak PFET and > Strong NFET, so they know they will not get stuck in no-mans land with > part variations. > > -jg- Hide quoted text - > > - Show quoted text -My coworker did suggest setting the drive to the lowest setting. I assume he's done this on past designs... I've just never seen it before.
Reply by ●November 1, 20072007-11-01
On Nov 1, 1:50 pm, Petrov_...@hotmail.com wrote:> On Nov 1, 2:25 pm, austin <aus...@xilinx.com> wrote: > > > Petrov, > > > Why are you trying to do this? > > > What is it supposed to protect the FPGA from? > > > Austin > > I'm not convinced I should be trying this, that's the problem. I've > always just enabled a weak pullup resistor on the input of a floating > pin. My coworker is trying to convince me that this approach offers > better noise immunity when nothing is connected to the input pin. > > The thing is, this input feeds a two-stage synchronizer... I would > think that alone would eliminate most noise to the synchronous logic > that follows.So are you saying that the input to your synchronizer would be floating??? -Dave Pollum
Reply by ●November 1, 20072007-11-01
On Nov 1, 2:55 pm, Dave Pollum <vze24...@verizon.net> wrote:> On Nov 1, 1:50 pm, Petrov_...@hotmail.com wrote: > > > > > > > On Nov 1, 2:25 pm, austin <aus...@xilinx.com> wrote: > > > > Petrov, > > > > Why are you trying to do this? > > > > What is it supposed to protect the FPGA from? > > > > Austin > > > I'm not convinced I should be trying this, that's the problem. I've > > always just enabled a weak pullup resistor on the input of a floating > > pin. My coworker is trying to convince me that this approach offers > > better noise immunity when nothing is connected to the input pin. > > > The thing is, this input feeds a two-stage synchronizer... I would > > think that alone would eliminate most noise to the synchronous logic > > that follows. > > So are you saying that the input to your synchronizer would be > floating??? > -Dave Pollum- Hide quoted text - > > - Show quoted text -No... it would still have the weak pullup enabled.
Reply by ●November 1, 20072007-11-01
Petrov, I can see no reason to do what your co-worker is suggesting, unless there are IOs very near this input, and those IOs are switching with large, and strong, currents (like LVCMOS 24 mA FAST, or PCI bus). The above assumes that this input is only weakly driven. If there is a strong driver to this input, then the only concern is if there is so much cross-talk or bounce that a driven signal to this pin is upset (requires many tens of mA of coupling, or volts of bounce!). If there are nearby switching, and the concern is crosstalk or ground bounce, then the real solution is to do the simulations, and either use the right part (like the V4 or V5 with the SpaseChevron(tm) package which minimizes crosstalk and bounce by a factor of 7.5 over other solutions), or ground the pins on either side of the input (which is another way to limit the crosstalk and bounce on the sensitive pin). Your friend's idea may not harm the output (it will not), but it won't really do what you want, either (deal with crosstalk or bounce). Austin
Reply by ●November 1, 20072007-11-01
Similar structures can be used for contact de-bouncing. Use a single-pole double-throw switch, connect the two poles to Vcc and ground, and the moving arm to the FPGA input/output. When input senses a Low, make the output drive low. When the input senses High, make the output drive High. The switch easily overrides the output driver (make it weak), and the current spike lasts only a few nanoseconds. Doesn't work with a single- throw switch... Peter Alfke On Nov 1, 10:26 am, Petrov_...@hotmail.com wrote:> Has anyone implemented a circuit similar to the one below? > > VCC > + > | > .---------------o > | | > | | > | .-. > | | | > | | | weak pullup > | '-' > | | > | | > | .-----o > | | | ----- > | |\| | | | > --------| >-----|-------| PIN | > |/ | | | > | ----- > | > | floating > | or > | GND > /| | > To Internal Fpga Logic <---------< |------- > \| > (created by AACircuit v1.28.6 beta 04/19/05www.tech-chat.de) > > When the input pin is floating, the weak pullup causes the output > buffer to drive Vcc out, negating any extraneous noise that may exist > on the external line. > > When the input pin is driven to ground, the buffer momentarily tries > driving Vcc to ground but stops once the tristate is disabled. > > I've always just used a weak pullup on the input (no tristate buffer > at all) but another engineer in our group says this is a good way to > protect input pins from noise on undriven inputs. I'm a little > concerned about the brief period of time when the tristate buffer is > driving ground but he assures me that the fpga can handle it. > > Do you agree?
Reply by ●November 2, 20072007-11-02
This looks like "voodoo design" to me. See http://foldoc.org/?voodoo+programming for the software equivalent. If you know what the problem really is, design for that. Use series or parallel termination to mitigate ground-bounce, for instance.
