negative hold time

What is negative hold time and what does it specify physically? 

Thanks in advance

rgds,
prav

On 10 Feb 2004 01:32:42 -0800, praveenkn123@yahoo.com (prav) wrote:

>What is negative hold time and what does it specify physically? 

Hold is, as you might know, how long data needs to be stable after the
edge of the clock. There is nothing tricky about a negative hold value
which suggests electrons going back in time. It just means that
internally to the flop, the data has much more delay to the sampler
than the clock. If you think about how you fix a hold violation, it
becomes clearer: you add a delay to the data input of the flop. A flop
with negative hold requirement has some delay added to the data path
already.

Muzaffer Kal wrote:

> On 10 Feb 2004 01:32:42 -0800, praveenkn123@yahoo.com (prav) wrote:
> 
> 
>>What is negative hold time and what does it specify physically? 
> 
> 
> Hold is, as you might know, how long data needs to be stable after the
> edge of the clock. There is nothing tricky about a negative hold value
> which suggests electrons going back in time. It just means that
> internally to the flop, the data has much more delay to the sampler
> than the clock. If you think about how you fix a hold violation, it
> becomes clearer: you add a delay to the data input of the flop. A flop
> with negative hold requirement has some delay added to the data path
> already.
> 
In case it's not obvious, the implication of this is that the input signal can change _before_ the flip-flop is clocked.  The difference in time between doing this and receiving the clock is the same as the magnitude of the negative hold time.

Charles B. Cameron

Let me blame T.I. for inventing (in the late 'sixties) the stupid name
"Hold Time", when we are really talking about the latest possible
instant of Set-Up Time.

Any D-flip-flop has an extremely tiny timing window (femtoseconds wide),
where it takes a snapshot of the D-input and generates either Q or Qbar.
The exact position (in time) of this tiny window with respect to the
clock edge is a function of processing, temperature and Vcc. 

The earliest possible position is specified as Set-up-time. The latest
possible position is (unfortunarely) specified as Positive Hold Time if
it is later than the clock edge, and as Negative Hold Time if it is
before the clock edge.

It would be so much nicer if we used only one parameter name, and called
the two extremes the max and the min value of the set-up time. I lost
that battle 30 years ago. It still smarts every time I hear "Hold Time"
.   :-(

Peter Alfke
=======================
"Charles B. Cameron" wrote:
> 
> Muzaffer Kal wrote:
> 
> > On 10 Feb 2004 01:32:42 -0800, praveenkn123@yahoo.com (prav) wrote:
> >
> >
> >>What is negative hold time and what does it specify physically?
> >
> >
> > Hold is, as you might know, how long data needs to be stable after the
> > edge of the clock. There is nothing tricky about a negative hold value
> > which suggests electrons going back in time. It just means that
> > internally to the flop, the data has much more delay to the sampler
> > than the clock. If you think about how you fix a hold violation, it
> > becomes clearer: you add a delay to the data input of the flop. A flop
> > with negative hold requirement has some delay added to the data path
> > already.
> >
> In case it's not obvious, the implication of this is that the input signal can change _before_ the flip-flop is clocked.  The difference in time between doing this and receiving the clock is the same as the magnitude of the negative hold time.
> 
> Charles B. Cameron

Peter Alfke wrote:

> Let me blame T.I. for inventing (in the late 'sixties) the stupid name
> "Hold Time", when we are really talking about the latest possible
> instant of Set-Up Time.

Really ?!

And I thought the Window between Setup and Hold is where the
input signal is NOT supposed to change (e.g. remain stable) !

> Any D-flip-flop has an extremely tiny timing window (femtoseconds wide),
> where it takes a snapshot of the D-input and generates either Q or Qbar.
> The exact position (in time) of this tiny window with respect to the
> clock edge is a function of processing, temperature and Vcc.

Depending on the clock transition time the window can be larger
or smaller (and is also of course process dependent). 

Hmm, all flops I have seen generate both Q and Qbar.

> The earliest possible position is specified as Set-up-time. The latest
> possible position is (unfortunarely) specified as Positive Hold Time if
> it is later than the clock edge, and as Negative Hold Time if it is
> before the clock edge.

Actually the latest possible change of the data is
Setup time, and the earlist possible change is Hold Time.

> It would be so much nicer if we used only one parameter name, and called
> the two extremes the max and the min value of the set-up time. I lost
> that battle 30 years ago. It still smarts every time I hear "Hold Time"
> .   :-(
> 
> Peter Alfke


rudi
========================================================
   ASICS.ws   ::: Solutions for your ASIC/FPGA needs :::
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Rudi,

Yawn.......

Bob


"Rudolf Usselmann" <russelmann@hotmail.com> wrote in message
news:c0cql4$vb7$1@nobel2.pacific.net.sg...
> Peter Alfke wrote:
>
> > Let me blame T.I. for inventing (in the late 'sixties) the stupid name
> > "Hold Time", when we are really talking about the latest possible
> > instant of Set-Up Time.
>
> Really ?!
>
> And I thought the Window between Setup and Hold is where the
> input signal is NOT supposed to change (e.g. remain stable) !
>
> > Any D-flip-flop has an extremely tiny timing window (femtoseconds wide),
> > where it takes a snapshot of the D-input and generates either Q or Qbar.
> > The exact position (in time) of this tiny window with respect to the
> > clock edge is a function of processing, temperature and Vcc.
>
> Depending on the clock transition time the window can be larger
> or smaller (and is also of course process dependent).
>
> Hmm, all flops I have seen generate both Q and Qbar.
>
> > The earliest possible position is specified as Set-up-time. The latest
> > possible position is (unfortunarely) specified as Positive Hold Time if
> > it is later than the clock edge, and as Negative Hold Time if it is
> > before the clock edge.
>
> Actually the latest possible change of the data is
> Setup time, and the earlist possible change is Hold Time.
>
> > It would be so much nicer if we used only one parameter name, and called
> > the two extremes the max and the min value of the set-up time. I lost
> > that battle 30 years ago. It still smarts every time I hear "Hold Time"
> > .   :-(
> >
> > Peter Alfke
>
>
> rudi
> ========================================================
>    ASICS.ws   ::: Solutions for your ASIC/FPGA needs :::
> ..............::: FPGAs * Full Custom ICs * IP Cores :::
> FREE IP Cores -> http://www.asics.ws/  <- FREE EDA Tools

Besides some meaningless semantic quibbling, Rudi's answer indicated
basic conceptual differences. 
A component data sheet should have a component-centric view: The
flip-flop has a window in time during which the D-input must be stable,
to guarantee predictable operation. This window has an early edge
(commonly called set-up time, often specified as a min, but I would call
it a max), and it has a late edge (commonly called positive hold time
when it is later than the clock edge, negative hold time when it is
before the clock edge. I would like to call it the min set-up time, but
it's too late to bring sanity to this issue).

Whether something is a min or a max depends on your perspective.
With a bridge over a highway, the  "14 feet" specification is a min for
the bridge builder, but a max for the truck driver...

Much of this is semantics, but semantics can interfere with
understanding, sometimes.
Peter Alfke


Rudolf Usselmann wrote:
> 
> Peter Alfke wrote:
> 
> > Let me blame T.I. for inventing (in the late 'sixties) the stupid name
> > "Hold Time", when we are really talking about the latest possible
> > instant of Set-Up Time.
> 
> Really ?!
> 
> And I thought the Window between Setup and Hold is where the
> input signal is NOT supposed to change (e.g. remain stable) !
> 
> > Any D-flip-flop has an extremely tiny timing window (femtoseconds wide),
> > where it takes a snapshot of the D-input and generates either Q or Qbar.
> > The exact position (in time) of this tiny window with respect to the
> > clock edge is a function of processing, temperature and Vcc.
> 
> Depending on the clock transition time the window can be larger
> or smaller (and is also of course process dependent).
> 
> Hmm, all flops I have seen generate both Q and Qbar.
> 
> > The earliest possible position is specified as Set-up-time. The latest
> > possible position is (unfortunarely) specified as Positive Hold Time if
> > it is later than the clock edge, and as Negative Hold Time if it is
> > before the clock edge.
> 
> Actually the latest possible change of the data is
> Setup time, and the earlist possible change is Hold Time.
> 
> > It would be so much nicer if we used only one parameter name, and called
> > the two extremes the max and the min value of the set-up time. I lost
> > that battle 30 years ago. It still smarts every time I hear "Hold Time"
> > .   :-(
> >
> > Peter Alfke
> 
> rudi
> ========================================================
>    ASICS.ws   ::: Solutions for your ASIC/FPGA needs :::
> ..............::: FPGAs * Full Custom ICs * IP Cores :::
> FREE IP Cores -> http://www.asics.ws/  <- FREE EDA Tools

Peter Alfke wrote:
> 
> Besides some meaningless semantic quibbling, Rudi's answer indicated
> basic conceptual differences.
> A component data sheet should have a component-centric view: The
> flip-flop has a window in time during which the D-input must be stable,
> to guarantee predictable operation. This window has an early edge
> (commonly called set-up time, often specified as a min, but I would call
> it a max), and it has a late edge (commonly called positive hold time
> when it is later than the clock edge, negative hold time when it is
> before the clock edge. I would like to call it the min set-up time, but
> it's too late to bring sanity to this issue).
> 
> Whether something is a min or a max depends on your perspective.
> With a bridge over a highway, the  "14 feet" specification is a min for
> the bridge builder, but a max for the truck driver...
> 
> Much of this is semantics, but semantics can interfere with
> understanding, sometimes.
> Peter Alfke

I don't know if any further comment is warrented or valuable, but I am
waiting for a download and thought I would post my 2 cents worth.  

I agree that the data sheet should be "component" centric.  But this is
normally done in terms of the interface.  The internal sampling of the
data input is what is going on, but that is not relevant given occam's
razor.  All the user needs to know is to maintain the data input stable
during a timing window.  Using one set of terms vs. the other does not
make the mechanics more clear in my point of view.  

I agree that the basis of this timing window is not clearly understood
by many engineers.  The way to improve the understanding is to have the
data sheets (or app notes) clearly explain the basis for the window (and
how it is measured) rather than just leaving it up to the engineer to
try to figure out what the data sheet writer is trying to spec.  I often
have trouble figuring out just what a spec is trying to say.  Perhaps a
JEDEC, EIA or other standards body could help by defining measurement
terms, what they are measuring and how they are measured?  

I especially find it interesting (not in a good way) when the spec I am
looking for is not in a data sheet, but instead a similar one is given
in its place.  For example, when I am looking for max static current
draw over temperature and I am given a typical current at 25C.  What is
the designer trying to tell me?  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

rickman wrote:
>  For example, when I am looking for max static current
> draw over temperature and I am given a typical current at 25C.  What is
> the designer trying to tell me?

Here is an explanation for that typical number:
In the olden days, static current was extremely low, microamps or a few
milliamps, and was usually swamped out by the dynamic power consumption.

So the argument went this way: 
If the part is hot because it is working hard, running with a fast
clock, nobody really cares about the leakage current. Even if it's
higher than the room temp spec, it is still an insignificant part of the
total current that made the chip get so hot.

When the part is not working hard, it will be near room temperature, and
because of the lack of dynamic power, the static current is a standby
value, and may be important. And everybody knows that leakage current
doubles for every 10 degree C increase in temperature. (The newly
increased leakage current is actually rising less dramatically).

With the recent dramatic increase in leakage current (by orders of
magnitude), that old reasoning may have to be revised...

Peter Alfke

Peter Alfke wrote:
> rickman wrote:
> 
>> For example, when I am looking for max static current
>>draw over temperature and I am given a typical current at 25C.  What is
>>the designer trying to tell me?
> 
> 
> Here is an explanation for that typical number:
> In the olden days, static current was extremely low, microamps or a few
> milliamps, and was usually swamped out by the dynamic power consumption.
> 
> So the argument went this way: 
> If the part is hot because it is working hard, running with a fast
> clock, nobody really cares about the leakage current. Even if it's
> higher than the room temp spec, it is still an insignificant part of the
> total current that made the chip get so hot.
> 
> When the part is not working hard, it will be near room temperature, and
> because of the lack of dynamic power, the static current is a standby
> value, and may be important. And everybody knows that leakage current
> doubles for every 10 degree C increase in temperature. (The newly
> increased leakage current is actually rising less dramatically).
> 
> With the recent dramatic increase in leakage current (by orders of
> magnitude), that old reasoning may have to be revised...

... and designs need to consider complete power removal of those hungry 
devices during sleep times, which moves away from a single chip solution..

> 
> Peter Alfke

  I think rickman was asking about TYP vs MAX ?
Typical appears on a data sheet for many reasons :
- It's a better sounding number  (don't laugh..)
- It's easier/quicker to derive than a MAX corner value.
- It's also usefull for average battery life calculations.

but sometimes, customers want to know worst case battery life,
and they may even be using batteries good enough to spec that over
temperature. So they need a corresponding chip value.

If the spec omits MAX, the designer could be trying to say
any or all of :
- The silicon is so new, we don't know this number yet
- Our test coverage could not guarantee this on all devices
- We do not bother to test it
- A few devices have this very high, and we are unsure why
- Why does that number matter again ?

  The new Lattice 4000 family, and Xilinx Coolrunner II do seem
to have good Typ, and Max static Icc specs, so perhaps
those customers are more demanding ?

  Personally, I prefer to see Icc vs Temp plots, and in the old
days of data sheets, they would plot Typ and Max on the same graph!


-jg