Global Reset using Global Buffer

Hello Group

I=B4ve read a lot about resets and I=B4ve decided that for my designs, an
asynchronous solution with a synchronous source is a better solution.
No discussions here, this is a personal (almost religious) choice.

Now, what I=B4ve read about using a global line as reset line, i think
it was on a discussion "on no, reset again" (something like that). So
I had tried several times to use a Global Buffer for my Global reset.
I can use the buffer, but instead of using the global lines, it uses
regular route lines wich ends ina a great reset skew.

Giving more details, I instantiate the buffer, I can see it on FPGA
Editor but it do not use the global lines. The fpga is an Spartan3,
for information.

Does anyone knows how to force the use of one global buffer (and the
global lines) for my async reset?

You can't use a global clock line as a reset,

The tools realize there is no way to route a logic signal on the global
clock line, so it does it the best way it can.

In V5, we added the necessary mux wiring so a global line could be used
for a logic signal.

As far as "global reset" is concerned, there is a nice series of
articles by Ken Chapman on the subject, but right now we are moving them
to a new location.

http://209.85.173.104/search?q=cache:kUSKmhw7emUJ:www.xilinx.com/xlnx/xweb/xil_tx_printfriendly.jsp%3FiLanguageID%3D1%26category%3D%26sGlobalNavPick%3D%26sSecondaryNavPick%3D%26multPartNum%3D1%26sTechX_ID%3Dkc_smart_reset+%22ken+chapman%22+global+reset&hl=en&ct=clnk&cd=2&gl=us

it is still cached on google, read it.

http://tinyurl.com/3bj53s

a smaller length link.

Austin

Hello,

Thanks for your reply.

Well, just like I said before, reset, global or not, sync or async is
not a point here. I humbly ask that this discussion to be in an
appropriante topic (there are several good discussions about it).

Back to my original question: sou, in V5 you're able to route logic
through the global lines, by instantiating the BUFG is that right?
I've done this. But the problem is: after the buffer, it still uses
regular routing lines and do not use the global ones.

Be a reset or not, can that be done to Spartan3? Can I force de route
after the BUFG to use globallines?

Regards,

On Nov 27, 1:59 pm, austin <aus...@xilinx.com> wrote:
> You can't use a global clock line as a reset,
>
> The tools realize there is no way to route a logic signal on the global
> clock line, so it does it the best way it can.
>
> In V5, we added the necessary mux wiring so a global line could be used
> for a logic signal.
>
> As far as "global reset" is concerned, there is a nice series of
> articles by Ken Chapman on the subject, but right now we are moving them
> to a new location.
>
> http://209.85.173.104/search?q=cache:kUSKmhw7emUJ:www.xilinx.com/xlnx...
>
> it is still cached on google, read it.
>
> http://tinyurl.com/3bj53s
>
> a smaller length link.
>
> Austin

What about "no" do you not understand?

No, you cannot use global resources for a logic signal in S3.

Yes, you can use a global clock for a logic signal in V5, but the entry
into the resource, and the exit from that resource may use additional
local routes (depending on what the logic signal is connected to/from).

You missed the entire issue of Ken's note:  asynchronous resets may
"break" synchronous circuits.  Since we don't support any asynchronous
circuits in the FPGA (everything assumes a synchronous logic design
flow, and we support no asynchronous logic synthesis), I think you may
be confused.

Austin

austin writes:
> No, you cannot use global resources for a logic signal in S3.

I've heard you say that before, and I don't dispute it, but I'm curious
as to the reason.  How does the S3 "know" whether the signal I've got
driving a global clock net is actually a clock?  Is there a minimum
frequency for the clock net?  I don't see one in the datasheet.

Eric

Eric Smith wrote:
> austin writes:
>> No, you cannot use global resources for a logic signal in S3.
> 
> I've heard you say that before, and I don't dispute it, but I'm curious
> as to the reason.  How does the S3 "know" whether the signal I've got
> driving a global clock net is actually a clock?  Is there a minimum
> frequency for the clock net?  I don't see one in the datasheet.

It's not a case of classifying the input as a "clock", but one of "you
can't get there from here".  The global clock nets go to clock pins, if
your destination is something other than a clock pin then it has to
"hop off" and use the regular routing resources to get there.

Ed McGettigan
--
Xilinx Inc.

Ed McGettigan wrote:
> It's not a case of classifying the input as a "clock", but one of "you
> can't get there from here".  The global clock nets go to clock pins, if
> your destination is something other than a clock pin then it has to
> "hop off" and use the regular routing resources to get there.

Thanks for the explanation; that's certainly a very good reason to not
try to use the clock net for something else.

I thought 2 uses for a global line, as reset and clock enable, because
my application DO require both. By the way, I=B4m not confused about
reset.

It's not an issue about using the buffer. It does route my signal,
whatever it=B4s source it is, to a global buffer (I can see that on FPGA
EDITOR) but then, it indeed "jumps" to regular lines after the buffer.
So, I thought that might there is someway to force the route through
global lines, because be it a clock or not, every signal connects to
CLB using a matrix. It could do that for anysignal. Couldn't it?

No, but it seems to me that this is imposed by the PAR tool. My point
that the clock input for every FF on the FPGA can be any signal on the
design, a bad, but possible design pratice. The same for enable and
reset.
So, the limitation is not on the interconnect matrix, because ALL
signals that enter a LUT or FF comes from there.

On Nov 27, 10:58 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
> Eric Smith wrote:
> > austin writes:
> >> No, you cannot use global resources for a logic signal in S3.
>
> > I've heard you say that before, and I don't dispute it, but I'm curious
> > as to the reason.  How does the S3 "know" whether the signal I've got
> > driving a global clock net is actually a clock?  Is there a minimum
> > frequency for the clock net?  I don't see one in the datasheet.
>
> It's not a case of classifying the input as a "clock", but one of "you
> can't get there from here".  The global clock nets go to clock pins, if
> your destination is something other than a clock pin then it has to
> "hop off" and use the regular routing resources to get there.
>
> Ed McGettigan
> --
> Xilinx Inc.

Rgamer wrote:
> I thought 2 uses for a global line, as reset and clock enable, because
> my application DO require both. By the way, I�m not confused about
> reset.
> 
> It's not an issue about using the buffer. It does route my signal,
> whatever it�s source it is, to a global buffer (I can see that on FPGA
> EDITOR) but then, it indeed "jumps" to regular lines after the buffer.
> So, I thought that might there is someway to force the route through
> global lines, because be it a clock or not, every signal connects to
> CLB using a matrix. It could do that for anysignal. Couldn't it?
> 
> No, but it seems to me that this is imposed by the PAR tool. My point
> that the clock input for every FF on the FPGA can be any signal on the
> design, a bad, but possible design pratice. The same for enable and
> reset.
> So, the limitation is not on the interconnect matrix, because ALL
> signals that enter a LUT or FF comes from there.


In FPGA Editor, if you click on the interconnect matrix where the global 
lines feed each CLB, each bubble that connects to a global line - when 
clicked on - will highlight the paths that connection can feed.  They 
are all clock lines, no reset.  If you highlight the bubble connected to 
the slice clock lines, you'll see where the clock can get its signal.

Through the CLB interconnect matrix, the global lines can only feed 
clocks (at least in families before V5).

The limitation IS the interconnection matrix.  Why do you believe otherwise?

> In FPGA Editor, if you click on the interconnect matrix where the global
> lines feed each CLB, each bubble that connects to a global line - when
> clicked on - will highlight the paths that connection can feed.  They
> are all clock lines, no reset.  If you highlight the bubble connected to
> the slice clock lines, you'll see where the clock can get its signal.
>
> Through the CLB interconnect matrix, the global lines can only feed
> clocks (at least in families before V5).

Using global lines for reset should work in Virtex4 as well.

Cheers,
Jim