Gnd plane coupling with DDR routing from FPGA <-> DDR?

Hopefully some of you guys who have gone through this can
comment...

We're doing our first board with a couple of DDRs and have a
query with ground plane coupling when routing the signals out
of the FPGA.

We're hoping to get away with a 6 layer board so the stack is..

sig1
GND
sig2
sig3
PWR
sig4

Any signals that're routed from the FPBA ball to sig4 won't have
the same good GND return paths to the FPGA that those coming out
on sig1/sig2 will have.

We're aiming to run the interface at ~2* 120MHz.

We don't have any simulation tools so are having to design using best
practice.

We can place a GND island in on the PWR layer under the FPGA/DDR
with plenty of vias stitching it up to the 'real' GND plane, but
this will make the PWR routing more difficult.

Does this matter, will the difference in GND coupling be a problem?

Some of the app notes we've read suggest that the track impedance
isn't too much of a problem.


Thanks for any pointers,


Nial

On Wed, 28 Nov 2007 10:06:22 -0000, "Nial Stewart"
<nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote:

>Hopefully some of you guys who have gone through this can
>comment...

I haven't yet, but I'm asking myself the same sort of questions for the
same sort of reasons.

>We're hoping to get away with a 6 layer board so the stack is..

Just an opinion.

While the board may be routable on 6 layers ... 

check the incremental cost of 8 layers over 6. Sometimes it's 10% or
less. 

That gives you a second ground plane and allows you to improve power
distribution.

Unless this is a HIGHLY cost-sensitive product, that looks like a good
investment to me, given the cost of the time involved in engineering a
solution any more closely.

- Brian

Nial,

Get a Signal Integrity Tool.

The money you spend on that is recovered by NOT having to respin your
pcb and first assembly run ONE TIME.

For something that has guaranteed payback, for the cost of a respin in
materials alone (does not even include your time, the pcb designer's
time, your cost of lost opportunity being late to market...) why do
people choose to suffer?

Are you a masochist?  Do you enjoy pain?  Or are you a sadist?  Do you
enjoy causing pain to others?

I suppose if I wanted revenge on a horrible boss, I would just follow
their directions, but what is the fun in that?  Go work for someone who
has a brain.

Austin

"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote in 
message news:5r4stdF12jom4U1@mid.individual.net...

>
> We can place a GND island in on the PWR layer under the FPGA/DDR
> with plenty of vias stitching it up to the 'real' GND plane, but
> this will make the PWR routing more difficult.
>
> Does this matter, will the difference in GND coupling be a problem?
>
>
> Nial
>

I would never split a plane except as a last resort (unless you can sandwich 
it between two solid planes - I often use a four layer GND, split power, 
split power, GND sandwich in the middle of 16-20 layer boards), because of 
the issues with traces crossing the split. If you must stick to six layers 
then you need to make the power plane look like a ground plane by ensuring 
that there are adequate decoupling capacitors spread uniformly across the 
board, such that no point on the board is more than some short distance from 
a capacitor. The AC return current can flow along the power plane and 
through the capacitor to ground. Of course, you want to reduce the 
inductance so use 0402 or 0603 parts with vias very close to the pads. 

"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk>
wrote:

>Hopefully some of you guys who have gone through this can
>comment...
>
>We're doing our first board with a couple of DDRs and have a
>query with ground plane coupling when routing the signals out
>of the FPGA.
>
>We're hoping to get away with a 6 layer board so the stack is..
>
>sig1
>GND
>sig2
>sig3
>PWR
>sig4
>
>Any signals that're routed from the FPBA ball to sig4 won't have
>the same good GND return paths to the FPGA that those coming out
>on sig1/sig2 will have.
>
>We're aiming to run the interface at ~2* 120MHz.

I have designed a similar 4 layer board which runs DDR at 100MHz. As
long as the traces between the FPGA and the DDR memory do not cross
plane borders, you'll probably be fine. In my design I optimized the
connections so I did have at most one via close to the FPGA pin in
traces between the FPGA and DDR. 

-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

On Nov 28, 5:06 am, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
> Hopefully some of you guys who have gone through this can
> comment...
>
> We're doing our first board with a couple of DDRs and have a
> query with ground plane coupling when routing the signals out
> of the FPGA.
>
> We're hoping to get away with a 6 layer board so the stack is..
>
> sig1
> GND
> sig2
> sig3
> PWR
> sig4
>
Power and ground are not going to be forming a very good capacitor to
supply power so you're making a big compromise right there, it won't
be a really low inductance pathway to deliver power to the parts on
the board.  Ideally you'd like to have two more layers, move PWR up to
be underneath GND and then mirror that on the bottom side (i.e. sig1,
GND, PWR, sig2, sig3, PWR, GND, sig4).  Whether your 6 layer bites you
or not will depend entirely on how much switching is going on and how
demanding the parts are.  I recently consulted on a design that had
the above type of stackup and the PCB was unable to deliver enough
3.3V to the FPGA and would cause it to functionally upset, the board
failed.  Adding the planes and putting power adjacent to ground was
the biggest impact in the fix, other remedies that were tried to band
aid the boards while waiting for the improved stackup design had only
marginal impact.

> Any signals that're routed from the FPBA ball to sig4 won't have
> the same good GND return paths to the FPGA that those coming out
> on sig1/sig2 will have.
As long as you're not talking about signals having to cross a break in
the power plane itself, being adjacent to the cut up power plane is
not much different.  It all comes down to how much copper is on that
plane adjacent to the signal.  The electromagnetic field does not care
the voltage level on  the hunk of metal that it runs into first.

>
> We're aiming to run the interface at ~2* 120MHz.
>
Is that 2 DDRs at 120 MHz?  Or 240 MHz?

> We don't have any simulation tools so are having to design using best
> practice.
>
If you can't spring for si tools, then I'd suggest the following
resources that you should peruse in besides just this particular
newsgroup
1. "Right the First Time: A Practical Handbook on High Speed PCB
Design and System Design".  Volumes 1 and 2, by Lee W. Ritchey.  Each
will set you back about $90USD I think but they are both well worth
it.  Can be purchased from speedingedge.com (I have no financial or
other interest in the book or the Speeding Edge company, this is just
a recommendation for what I've found to be an excellent resource).

2.  http://www.freelists.org/list/si-list which is a newsgroup
dedicated to signal integrity issues.  Post your questions up there
and you'll get well informed responses from a number of experts.
comp.arch.fpga contains some people that know what they're talking
about and others that only think they know.  In fairness though, this
FPGA newsgroup has a different focus that handles issues that run
through the whole spectrum of issues related to FPGA design starting
from synthesis/simulation tool problems, coding formats, downloading,
component packaging and PCB design, etc.

> We can place a GND island in on the PWR layer under the FPGA/DDR
> with plenty of vias stitching it up to the 'real' GND plane, but
> this will make the PWR routing more difficult.
>
Putting the island in won't help at all.

Kevin Jennings

"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote in 
message news:5r4stdF12jom4U1@mid.individual.net...
> Hopefully some of you guys who have gone through this can
> comment...
>
> We're doing our first board with a couple of DDRs and have a
> query with ground plane coupling when routing the signals out
> of the FPGA.
>
> We're hoping to get away with a 6 layer board so the stack is..
>
> sig1
> GND
> sig2
> sig3
> PWR
> sig4
>
> Any signals that're routed from the FPBA ball to sig4 won't have
> the same good GND return paths to the FPGA that those coming out
> on sig1/sig2 will have.
>
> We're aiming to run the interface at ~2* 120MHz.
>
> We don't have any simulation tools so are having to design using best
> practice.
>
> We can place a GND island in on the PWR layer under the FPGA/DDR
> with plenty of vias stitching it up to the 'real' GND plane, but
> this will make the PWR routing more difficult.
>
> Does this matter, will the difference in GND coupling be a problem?
>
> Some of the app notes we've read suggest that the track impedance
> isn't too much of a problem.
>
>
> Thanks for any pointers,
>
>
> Nial
>
Hi Nial,

Wow, you got some strange answers! (IMHO, natch.) The same old chestnuts 
about PWR and GND planes being used as bypass capacitance. Waste of time. 
The tiny capacitance is no use to you as you have to attach the FPGA to it 
_VIA_ inductance. This is why FPGA companies embed bypass caps in the 
package. BTW, what PWR is on the plane? VCCO for your DDR bank? VCCINT?

Also, 16-20 layer boards? I guess it'll work, but I'm glad I'm not paying 
for it.

Good answers you got are, 'use two more layers', 'simulate', 'SI-LIST', and 
'use as few vias as possible'. Oh, and don't cross gaps in planes, but we 
all know that, right?

I'd do something like this:-

sig
gnd
sig
sig
gnd
sig

I'd route the powers on one or two of the internal layers. I'd use copper 
pours and/or little puddles of cu for each supply. I'd use X2Y caps backside 
of the FPGA for bypassing. (Google X2Y FPGA) If a fast signal changes its 
ground reference from one ground plane to another, I'd put a GND via nearby. 
Several fast signals can share a single ground via.

Austin's right, if you're a beginner you should certainly use a simulator. 
Maybe you can borrow one from somewhere? Any universities nearby? However, 
the 'two ground planes' design makes it considerably harder to get it wrong, 
especially at 120MHz.

HTH. Syms.

p.s. You did search back through CAF for previous threads, right? ;-)

"Symon" <symon_brewer@hotmail.com> wrote in message 
news:fikd12$uf7$1@aioe.org...
> Wow, you got some strange answers! (IMHO, natch.) The same old chestnuts 
> about PWR and GND planes being used as bypass capacitance. Waste of time. 
> The tiny capacitance is no use to you as you have to attach the FPGA to it 
> _VIA_ inductance. This is why FPGA companies embed bypass caps in the 
> package. BTW, what PWR is on the plane? VCCO for your DDR bank? VCCINT?
>

I disagree, as does most of the research done into the subject. The use of 
buried capacitance, typically by having adjacent power and ground planes 
separated by as small a distance as possible (2 thou is normal), has been 
shown to be very favorable when compared to discrete decoupling caps because 
although the capacitance is much lower the inductance is very much lower so 
the overall impedence is significantly lower. There is an article about it 
here: http://www.ddmconsulting.com/Design_Guides/bcguide.pdf

The requirement for discrete capacitors on the BGA substrate itself is a 
different matter. That is to compensate for the inductance of the BGA ball 
and tracking and is necessary regardless of how the board level decoupling 
is implemented. 

Nial Stewart wrote:
> Hopefully some of you guys who have gone through this can
> comment...
> 
> We're doing our first board with a couple of DDRs and have a
> query with ground plane coupling when routing the signals out
> of the FPGA.
> 
> We're hoping to get away with a 6 layer board so the stack is..
> 
> sig1
> GND
> sig2
> sig3
> PWR
> sig4
> 
I've had good results with :
sig1
sig2
GND
PWR
sig3
sig4

If you really need to, you can make the traces on sig1 and sig4 a little 
wider to keep the impedance near the right value.  Keeping GND and PWR 
planes close together helps.  If sig1 and sig2 are orthogonal, and same
for sig3 and sig4, there should be minimal crosstalk.  I have not done a
DDR memory, but signal integrity is signal integrity.

Jon

> We're aiming to run the interface at ~2* 120MHz.

I understand that as 120 MHz clock, 240 MHz data rate
during bursts.
Recently I had a similar case - processor (not FPGA),
which is in a 256 ball FPGA, 133 MHz clock/266 MHz data burst
rate.
 However, I was much more conservatiive with my stackup.
Instead of your

> sig1
> GND
> sig2
> sig3
> PWR
> sig4

I did 6 layers as well, but my stackup is:

signal
GND
PWR
PWR
GND
signal

Worked the first time, actually see the prototype
(very first one assembled, design for an external customer)
board here:

http://tgi-sci.com/y2demo/PICT3007sc.JPG .

The two DDRAMs (x16 each) are close to the board centre, easy
to spot.

Here is the bare board in some better detail:

http://tgi-sci.com/misc/PICT0605.JPG .

The board is routed at 6 mil most of the time which goes
down to somewhat over 4 mil for the worst case angular
ring and for traces between BGA pads (3 traces between a
pair of 1.27mm spaced pads/vias.
 Have used these rules on other boards as well, have never
failed me. Routing takes somewhat more head scratching (or is
it hear teraing... :-) ), but has always been doable.
 Now what do I do with a 0.8mm BGA (soon to be routed here,
never done so far) is yet to be seen... :-)

At these low speeds, buying signal integrity tools/consultants
will be a sheer waste. You need neither (although ask that on
the SI list and you will be overwhelmed by suggestions to
buy all things imaginable... make sure to ignore such advice,
the SI tool writers and SI consultants are pretty active on that
list).
Buy a tool by the usual criterion, that is, only if you know
exactly what you want the tool to do for you and if you
understand how it will do it.
 Buying a software blindly expecting it to solve your problems
will typically result in more, not less problems. Which does
not mean most people nowadays are not doing exactly that,
of course :-).

 Again, 120 MHz is nearly DC nowadays. You don't need any
fancy SI tools to do it.

Dimiter

------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------

On Nov 28, 12:06 pm, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
> Hopefully some of you guys who have gone through this can
> comment...
>
> We're doing our first board with a couple of DDRs and have a
> query with ground plane coupling when routing the signals out
> of the FPGA.
>
> We're hoping to get away with a 6 layer board so the stack is..
>
> sig1
> GND
> sig2
> sig3
> PWR
> sig4
>
> Any signals that're routed from the FPBA ball to sig4 won't have
> the same good GND return paths to the FPGA that those coming out
> on sig1/sig2 will have.
>
> We're aiming to run the interface at ~2* 120MHz.
>
> We don't have any simulation tools so are having to design using best
> practice.
>
> We can place a GND island in on the PWR layer under the FPGA/DDR
> with plenty of vias stitching it up to the 'real' GND plane, but
> this will make the PWR routing more difficult.
>
> Does this matter, will the difference in GND coupling be a problem?
>
> Some of the app notes we've read suggest that the track impedance
> isn't too much of a problem.
>
> Thanks for any pointers,
>
> Nial