Gnd plane coupling with DDR routing from FPGA <-> DDR?

"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote in 
message news:5r7gc7F12nc8dU1@mid.individual.net...
>
> Looking at the complexity/density/performance of a typical PC motherboard
> I'm still impressed at the price they knock them out for.
>
Hi Nial,
I doubt they press the 'autoroute' button on their PCB CAD tool!
Cheers, Syms. 

"David Spencer" <davidmspencer@verizon.net> wrote in message 
news:_YB3j.26538$XT.7448@trnddc01...
>
> It's not the frequency that matters, but rather the edge rate. It is the 
> behavior of the edges that are altered by the characteristics of a 
> transmission line. The frequency just indicates how often such edges 
> occur. This is why many older designs fail when a manufacturer introduces 
> a faster, die-shrunk, version of a part. Although the application is using 
> the part in the same way, the unavoidable change in edge rate can break a 
> previously working board.
>
Hi David,
To be technically correct (the best kind of correct!) it's not the edge 
rate, but the rise time. :-) I'm sure that's what you meant, I'm just being 
pedantic...
HTH, Syms. 

"Symon" <symon_brewer@hotmail.com> wrote in message 
news:fims50$arc$1@aioe.org...
> Hi David,
> To be technically correct (the best kind of correct!) it's not the edge 
> rate, but the rise time. :-) I'm sure that's what you meant, I'm just 
> being pedantic...
> HTH, Syms.
>
Or "fall time". ;)

The point I was trying to make (and which I'm still not sure Didi fully got) 
was that if a device is designed such that its outputs can operate at, say, 
200 MHz, then running that device at 1 MHz will not generally magically 
improve the signal integrity. 

On Nov 29, 7:25 pm, "David Spencer" <davidmspen...@verizon.net> wrote:
> "Symon" <symon_bre...@hotmail.com> wrote in message
> The point I was trying to make (and which I'm still not sure Didi fully got)
> was that if a device is designed such that its outputs can operate at, say,
> 200 MHz, then running that device at 1 MHz will not generally magically
> improve the signal integrity.

I got the point you made with your first post. In goes into details
I explicitly did not want to go into, because one does not need to
do it in this case, this is the essence of my point.
It can be detailed as "at 120 MHz DDR clock frequency edges
and generally related parts on the market are nearly as easy to use as
if
they were DC nowadays".
 I expected the "nowadays", put in context with
the links to some board photos I provided, to make the point obvious
enough.
Clearly you do have to treat transmission lines as such,
but no extra effort except keeping in mind you are doing that is
necessary.
 I hope my point is now clear enough :-).

BTW, how many persons do you know who have designed boards of
comparable complexity/density/speed to those I showed in the thread
who would have a problem getting the point you made (which says
it is not the frequency but the timing relationships which matter,
put in a more general way)? .... :-) :-)

Dimiter

------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------
http://www.flickr.com/photos/didi_tgi/sets/72157600228621276/

In fact the denser board - http://tgi-sci.com/misc/PICT3084.JPG - is
routed by me 7 years ago, with 100 MHz SDRAMs at the photo.

>
> news:fims50$arc$1@aioe.org...> Hi David,
> > To be technically correct (the best kind of correct!) it's not the edge
> > rate, but the rise time. :-) I'm sure that's what you meant, I'm just
> > being pedantic...
> > HTH, Syms.
>
> Or "fall time". ;)
>
> The point I was trying to make (and which I'm still not sure Didi fully got)
> was that if a device is designed such that its outputs can operate at, say,
> 200 MHz, then running that device at 1 MHz will not generally magically
> improve the signal integrity.

On Thu, 29 Nov 2007 08:57:26 -0000, "Nial Stewart"
<nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote:

>> I disagree, as does most of the research done into the subject. The use of buried capacitance, 
>> typically by having adjacent power and ground planes separated by as small a distance as possible 
>> (2 thou is normal), has been shown to be very favorable when compared to discrete decoupling caps 
>> because although the capacitance is much lower the inductance is very much lower so the overall 
>> impedence is significantly lower. There is an article about it here: 
>> http://www.ddmconsulting.com/Design_Guides/bcguide.pdf
>
>David,
>
>I too am skeptical about the amount of decoupling that close GND/PWR plane
>coupling can provice.
>
>In that atricle above they quote 560pF/sq inch. Most BGAs are smaller
>than that.

It's not just the footprint under the bga that helps, it's the entire
plane.

I sometimes add a few SMA connector footprints to pc boards, so I can
TDR the power planes relative to the ground plane. It's amazing. A
typical power plane, on an unloaded board, looks like a perfect
capacitor to 20 GHz, with no evidence of reflections or edge effects.
Then if you start adding bypass caps *anywhere*, it just looks like a
bigger perfect capacitor.

I know one guy who doesn't use bypass caps at all, and his stuff works
too.

John

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message 
news:061vk3hncpn2man9udarrgt80b2lasfl97@4ax.com...
>
> I sometimes add a few SMA connector footprints to pc boards, so I can
> TDR the power planes relative to the ground plane. It's amazing. A
> typical power plane, on an unloaded board, looks like a perfect
> capacitor to 20 GHz, with no evidence of reflections or edge effects.
> Then if you start adding bypass caps *anywhere*, it just looks like a
> bigger perfect capacitor.
>
Hi John,
As we've discussed before, I think that would be a really useful experiment 
if this thread was about microwave engineering (say). Sadly, we're talking 
about FPGA PDSs. FPGAs don't have SMA connections to hook up their power 
supplies to a board's planes, so, altough interesting, I think the TDR 
experiment results aren't applicable in this case. It doesn't matter how 
amazing the capacitance quality is, you can't wire it to the silicon.
I still say, ditch the power planes, put the bypass caps (maybe X2Y types) 
on power puddles near the device, that'll work great. This save planes, 
which you can use as ground planes. This topology allows the designer to 
filter the supplies near the FPGA to isolate it. If you believe that your 
high speed signals work better with a return path, and I know some folk on 
CAF apparently don't, then when these signals swap reference from one ground 
plane to another you can just use a ground via for the return path as 
opposed to the situation where a signal switches from ground referred to 
power plane referred, which costs a bypass cap and two vias and has much 
more inductance.
One thing from John's post I do find intriguing is his mate who doesn't use 
any bypass caps. I can quite believe that his stuff works just fine. I still 
think it's easier to get PDS right than wrong. Most designs will 'work'. 
That's why this subject is perfect for a usenet religious war!
HTH, Syms.

p.s. From experience, I know John likes to read links I post so he can offer 
his reasoned critique. I saw the comment about 'bypass caps *anywhere*' in 
his post, and so I eagerly await John's response to this.
http://www.x2y.com/bypass/method/does_position_matter.pdf
:-)

"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote in 
message news:5r7druF135mm3U1@mid.individual.net...
>
> I think you've said before that you've got away with routing power in like
> this with no problems.
>
Hi Nial,
I just re-read this bit, and would just like to clarify that it wasn't so 
much 'got away with' as 'had success with'! :-) It works out cheaper and 
performs better in terms of EMI, routability, SI over the whole board.

One more point, in the six layer stackup I suggested, I would make the 
centre core (between layers 3 and 4) thick, so that the signal layers 
1,3,4,6 are close to their reference planes. There's some stuff in this link 
that explains why better than I can. (It's applicable for regular caps as 
well as X2Y ones!)
http://www.x2y.com/bypass/mount/get_the_most.pdf
Cheers, Syms. 

> I know one guy who doesn't use bypass caps at all, and his stuff works
> too.


For FPGA designs with multiple syncronous fast IOs?




Nial 

> I still say, ditch the power planes, put the bypass caps (maybe X2Y types) on power puddles near 
> the device, that'll work great. This save planes, which you can use as ground planes. This 
> topology allows the designer to filter the supplies near the FPGA to isolate it. If you believe 
> that your high speed signals work better with a return path, and I know some folk on CAF 
> apparently don't, then when these signals swap reference from one ground plane to another you can 
> just use a ground via for the return path as opposed to the situation where a signal switches from 
> ground referred to power plane referred, which costs a bypass cap and two vias and has much more 
> inductance.

Symon,

You've posted useful snapshots of board desing before (ie to illustrate the
usefulness of micro-vias).

Any change of a screen shot of a board you've done using this technique to
illustrate things better?

We have an interrupted power plane with is _really_ well decoupled at the
FPGA and DDR so our current thinking is to use routinh on layers 1 3 and 6.


From another post...

> One more point, in the six layer stackup I suggested, I would make the centre core (between layers 
> 3 and 4) thick, so that the signal layers 1,3,4,6 are close to their reference planes. There's 
> some stuff in this link that explains why better than I can. (It's applicable for regular caps as 
> well as X2Y ones!)

Hmm, more expense specifying stack build up?

I think a 'normal' 6 layer stack uses relatively thick cores with thinner
pre-preg so layers 3 and 4 end up significantly nearer the planes at 2 and
5 that the top and bottom layer.

Bearing this in mind, if we're using a normal stack perhaps we should be
using the top and layers 3 and 4 to route out to the DDR.

Or again I'm worrying about things too much?

> Most designs will 'work'.

Hopefully.

> That's why this subject is perfect for a usenet religious war!

[panto] Oh no it's not [/panto].


Nial. 

"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote in 
message news:5ra56hF139idpU1@mid.individual.net...
>> inductance.
>
> Symon,
>
> You've posted useful snapshots of board desing before (ie to illustrate 
> the
> usefulness of micro-vias).
>
> Any change of a screen shot of a board you've done using this technique to
> illustrate things better?
>

I'll have to ask my client if it's ok.
>
> We have an interrupted power plane with is _really_ well decoupled at the
> FPGA and DDR so our current thinking is to use routinh on layers 1 3 and 
> 6.
>
So, just to be clear, how are you planning on connecting all your supplies? 
Vccint, Vcco for each bank, Vccaux, to use the Xilinx names. Do you have 
different voltages on some Vcco banks? I usually have 3.3 and 2.5 volt 
banks.
Cheers, Syms.