ISE WARNING Xst:647

On Nov 29, 8:36 am, Mark McDougall <ma...@vl.com.au> wrote:
> Hi,
>
> I have a design that works fine in Quartus.
>
> In the process of porting it to ISE, I'm getting a series of these
> warnings and can't for the life of me work out why...
>
> An example:
> WARNING:Xst:647 - Input <vblank> is never used.
>
> But it clearly _is_ being used!?! Same for all the other signals that it's
> complaining about.
>
> Normally I'd suspect a missing clock but that doesn't appear to be the
> case. (For the record the clock for this process isn't actually meeting
> all timing constraints at the moment.)
>
> Any tips would be appreciated - it's driving me (more) insane!
> Regards,
>
> --
> Mark McDougall, Engineer
> Virtual Logic Pty Ltd, <http://www.vl.com.au>
> 21-25 King St, Rockdale, 2216
> Ph: +612-9599-3255 Fax: +612-9599-3266



if u connect sub modules with each other (port connection),
and u dont use all signals in 2nd module, ISE ll issue that warning.
even if that port u use in submodules, but if it have no contribution
to your all logic, ISE ll give warning.
because during optimization ISE not create any hardware for unused
logic. (the logic which have no contribution to your path i.e input to
output).
if u also out ur warning ports through ur top module. then no warning
ll b issued.

Regards
Shahid