hey guys i hope u can help me out... i want to design a simple traffic
light controller according to the 4 states shown in the code below. my
only problem is that my signal state_reg is not changing form one
state to another. this is because the counter i included in the the
code as a process is not working. green to yellow time wait is 30 sec
and yellow to red is 5 sec. my clock period will be 5 sec. so can
anyone help me out
----------------------------------------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity TLC is
port(
clk,reset, sa, sb:in std_logic;
Ga, Ya, Ra, Gb, Yb, Rb:out std_logic
);
end TLC;
architecture Behavioral of TLC is
type state_type is (a, b, c, d);
signal state_reg, state_next: state_type;
signal Pre_Q, Q: std_logic_vector(3 downto 0);
signal count, clear: std_logic;
begin
-- behavior describe the counter
process(clk, count, clear)
begin
if (clear = '0') then
Pre_Q <= Pre_Q - Pre_Q;
elsif (clk='1' and clk'event) then
if (count = '1') then
Pre_Q <= Pre_Q + 1;
end if;
end if;
Q <= Pre_Q;
end process;
-- state register
process(clk,reset)
begin
if(reset='0') then
state_reg <= a;
elsif (clk'event and clk='1') then
state_reg <= state_next;
end if;
end process;
-- next state logic
process(state_reg,Q,sa,sb)
begin
case state_reg is
when a =>
if(sa = '1' and sb = '0')then
state_next <= a;
elsif (sa = '0' and sb = '1') then
count <= '1';
if(Q = "0110") then
state_next <= b;
end if;
end if;
when b =>
if(Q = "0111") then
state_next <= c;
count <= '0';
elsif(sa = '1') then
state_next <= b;
end if;
when c =>
if(sa = '0' and sb = '1') then
state_next <= c;
elsif (sa = '1' and sb ='0') then
clear <= '0';
count <= '1';
if(Q = "0110") then
state_next <= d;
end if;
end if;
when d =>
if(Q = "0111") then
state_next <= a;
count <= '0';
elsif(sb = '1') then
state_next <= d;
end if;
end case;
end process;
process (state_reg)
begin
Ga <= '1'; Ya <= '0'; Ra <= '0';
Gb <= '0'; Yb <= '0'; Rb <= '1';
case state_reg is
when a =>
when b =>
Ga <= '0';
Ya <= '1';
when c =>
Ya <= '0';
Ra <= '1';
Gb <= '1';
when d =>
Gb <= '0';
Yb <= '1';
end case;
end process;
end Behavioral;
--------------------------------------------------------------------------------------------------------------------------------------------------------
Traffic Light with counter
Started by ●November 30, 2007
Reply by ●November 30, 20072007-11-30
On Nov 30, 5:12 pm, tang <tarangpatel2elect...@gmail.com> wrote:> hey guys i hope u can help me out... i want to design a simple traffic > light controller according to the 4 states shown in the code below. my > only problem is that my signal state_reg is not changing form one > state to another. this is because the counter i included in the the > code as a process is not working. green to yellow time wait is 30 sec > and yellow to red is 5 sec. my clock period will be 5 sec. so can > anyone help me out > > ------------------------------------------------------------------------------------------------------------------------------------------------------------ > library ieee; > use ieee.std_logic_1164.all; > use ieee.std_logic_arith.all; > use IEEE.std_logic_unsigned.all; > > entity TLC is > port( > clk,reset, sa, sb:in std_logic; > Ga, Ya, Ra, Gb, Yb, Rb:out std_logic > ); > end TLC; > > architecture Behavioral of TLC is > > type state_type is (a, b, c, d); > signal state_reg, state_next: state_type; > signal Pre_Q, Q: std_logic_vector(3 downto 0); > signal count, clear: std_logic; > > begin > > -- behavior describe the counter > process(clk, count, clear) > begin > if (clear = '0') then > Pre_Q <= Pre_Q - Pre_Q; > elsif (clk='1' and clk'event) then > if (count = '1') then > Pre_Q <= Pre_Q + 1; > end if; > end if; > Q <= Pre_Q; > end process; > > -- state register > > process(clk,reset) > begin > if(reset='0') then > state_reg <= a; > elsif (clk'event and clk='1') then > state_reg <= state_next; > end if; > end process; > > -- next state logic > > process(state_reg,Q,sa,sb) > begin > > case state_reg is > when a => > if(sa = '1' and sb = '0')then > state_next <= a; > elsif (sa = '0' and sb = '1') then > count <= '1'; > if(Q = "0110") then > state_next <= b; > end if; > end if; > > when b => > > if(Q = "0111") then > state_next <= c; > count <= '0'; > elsif(sa = '1') then > state_next <= b; > end if; > > when c => > if(sa = '0' and sb = '1') then > state_next <= c; > elsif (sa = '1' and sb ='0') then > clear <= '0'; > count <= '1'; > if(Q = "0110") then > state_next <= d; > > end if; > end if; > > when d => > > if(Q = "0111") then > state_next <= a; > count <= '0'; > elsif(sb = '1') then > state_next <= d; > end if; > end case; > end process; > > process (state_reg) > begin > Ga <= '1'; Ya <= '0'; Ra <= '0'; > Gb <= '0'; Yb <= '0'; Rb <= '1'; > > case state_reg is > when a => > when b => > Ga <= '0'; > Ya <= '1'; > > when c => > Ya <= '0'; > Ra <= '1'; > Gb <= '1'; > > when d => > Gb <= '0'; > Yb <= '1'; > > end case; > > end process; > > end Behavioral; > ----------------------------------------------------------------------------------------------------------------------------------------------------------First, I would stongly suggest you use numeric_std instead of std_logic_arith, especially when you're learning, since it's the accepted standard. Next, remember that at the start of simulation, all of your std_logic signal and output values are 'U', or unspecified. Any operation you perform where one of the operands is 'U' will most likely return 'U', so at some point you've got to give them a concrete value if you want anything to happen. Also, in a case statement, if you want to cover multiple cases, use "when a | b =>", not "when a => when b =>". That's the way it's done in C, not VHDL. These aren't all the problems, but hopefully this will set you on the right track.
Reply by ●November 30, 20072007-11-30
"tang" <tarangpatel2electric@gmail.com> wrote in message news:48da85be-c67e-479c-8b6c-3824f5e98ee9@d61g2000hsa.googlegroups.com...> hey guys i hope u can help me out... i want to design a simple traffic > light controller according to the 4 states shown in the code below. my > only problem is that my signal state_reg is not changing form one > state to another. this is because the counter i included in the the > code as a process is not working. green to yellow time wait is 30 sec > and yellow to red is 5 sec. my clock period will be 5 sec. so can > anyone help me out >Hey tang, You should try comp.lang.vhdl . There are a bunch of blokes over there who _really_ know how sensitivity lists work. Ask for Mike xor Jonathan orif Jim. They're among the best at homework. Tell them I sent you. HTH., Syms. p.s. These days, 'traffic light vhdl' is at 159000 Google hits. Adding lumberjack to the search gets you down to a more sensible 39. Only two worse than adding omg ponies. (Thanks to Ben J. for that insight!) Be sure to turn off 'safe search'.
Reply by ●December 1, 20072007-12-01
On Sat, 1 Dec 2007 02:16:06 -0000, Symon wrote:>You should try comp.lang.vhdl . There are a bunch of blokes over there who >_really_ know how sensitivity lists work. Ask for Mike xor Jonathan orif >Jim. They're among the best at homework. Tell them I sent you. >HTH., Syms.Symon, you are A Very Bad Person. I can think of nations less tolerant and inclusive than ours where this sort of incitement to technical hatred could get you a stiff sentence (something along the lines of "This sentence is inflexible"?).>p.s. These days, 'traffic light vhdl' is at 159000 Google hits. Adding >lumberjack to the search gets you down to a more sensible 39. Only two worse >than adding omg ponies.[chokes on breakfast toast] Brilliant! -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
Reply by ●December 1, 20072007-12-01
There are a large number of ways you could do this. Personally I'm not a get fan of next state, current state, style you use but it does have it's followers. Staying with what you have I would check the asychronous (combinatorial) processes have complete sensativity lists. Your clocked processes I would make sure all statements lie with the clock and reset statements. Personally I would have a counter that reloaded with values linked to the transitions of the state machine and taking a count value relevant to the state being entered. The counter then counts down to zero and then the next state transition. If you make your counter integer type you don't need extra numerical type libraries. John Adair Enterpoint Ltd. - Home of Craignells The obsolete DIL solution. On 30 Nov, 22:12, tang <tarangpatel2elect...@gmail.com> wrote:> hey guys i hope u can help me out... i want to design a simple traffic > light controller according to the 4 states shown in the code below. my > only problem is that my signal state_reg is not changing form one > state to another. this is because the counter i included in the the > code as a process is not working. green to yellow time wait is 30 sec > and yellow to red is 5 sec. my clock period will be 5 sec. so can > anyone help me out > > ------------------------------------------------------------------------------------------------------------------------------------------------------------ > library ieee; > use ieee.std_logic_1164.all; > use ieee.std_logic_arith.all; > use IEEE.std_logic_unsigned.all; > > entity TLC is > port( > clk,reset, sa, sb:in std_logic; > Ga, Ya, Ra, Gb, Yb, Rb:out std_logic > ); > end TLC; > > architecture Behavioral of TLC is > > type state_type is (a, b, c, d); > signal state_reg, state_next: state_type; > signal Pre_Q, Q: std_logic_vector(3 downto 0); > signal count, clear: std_logic; > > begin > > -- behavior describe the counter > process(clk, count, clear) > begin > if (clear = '0') then > Pre_Q <= Pre_Q - Pre_Q; > elsif (clk='1' and clk'event) then > if (count = '1') then > Pre_Q <= Pre_Q + 1; > end if; > end if; > Q <= Pre_Q; > end process; > > -- state register > > process(clk,reset) > begin > if(reset='0') then > state_reg <= a; > elsif (clk'event and clk='1') then > state_reg <= state_next; > end if; > end process; > > -- next state logic > > process(state_reg,Q,sa,sb) > begin > > case state_reg is > when a => > if(sa = '1' and sb = '0')then > state_next <= a; > elsif (sa = '0' and sb = '1') then > count <= '1'; > if(Q = "0110") then > state_next <= b; > end if; > end if; > > when b => > > if(Q = "0111") then > state_next <= c; > count <= '0'; > elsif(sa = '1') then > state_next <= b; > end if; > > when c => > if(sa = '0' and sb = '1') then > state_next <= c; > elsif (sa = '1' and sb ='0') then > clear <= '0'; > count <= '1'; > if(Q = "0110") then > state_next <= d; > > end if; > end if; > > when d => > > if(Q = "0111") then > state_next <= a; > count <= '0'; > elsif(sb = '1') then > state_next <= d; > end if; > end case; > end process; > > process (state_reg) > begin > Ga <= '1'; Ya <= '0'; Ra <= '0'; > Gb <= '0'; Yb <= '0'; Rb <= '1'; > > case state_reg is > when a => > when b => > Ga <= '0'; > Ya <= '1'; > > when c => > Ya <= '0'; > Ra <= '1'; > Gb <= '1'; > > when d => > Gb <= '0'; > Yb <= '1'; > > end case; > > end process; > > end Behavioral; > ----------------------------------------------------------------------------------------------------------------------------------------------------------
Reply by ●December 1, 20072007-12-01
On Dec 1, 1:59 am, John Adair <g...@enterpoint.co.uk> wrote:> There are a large number of ways you could do this. Personally I'm not > a get fan of next state, current state, style you use but it does have > it's followers. > > Staying with what you have I would check the asychronous > (combinatorial) processes have complete sensativity lists. Your > clocked processes I would make sure all statements lie with the clock > and reset statements. > > Personally I would have a counter that reloaded with values linked to > the transitions of the state machine and taking a count value relevant > to the state being entered. The counter then counts down to zero and > then the next state transition. If you make your counter integer type > you don't need extra numerical type libraries. > > John Adair > Enterpoint Ltd. - Home of Craignells The obsolete DIL solution. > > On 30 Nov, 22:12, tang <tarangpatel2elect...@gmail.com> wrote: > > > > > > > hey guys i hope u can help me out... i want to design a simple traffic > > light controller according to the 4 states shown in the code below. my > > only problem is that my signal state_reg is not changing form one > > state to another. this is because the counter i included in the the > > code as a process is not working. green to yellow time wait is 30 sec > > and yellow to red is 5 sec. my clock period will be 5 sec. so can > > anyone help me out > > > ------------------------------------------------------------------------------------------------------------------------------------------------------------ > > library ieee; > > use ieee.std_logic_1164.all; > > use ieee.std_logic_arith.all; > > use IEEE.std_logic_unsigned.all; > > > entity TLC is > > port( > > clk,reset, sa, sb:in std_logic; > > Ga, Ya, Ra, Gb, Yb, Rb:out std_logic > > ); > > end TLC; > > > architecture Behavioral of TLC is > > > type state_type is (a, b, c, d); > > signal state_reg, state_next: state_type; > > signal Pre_Q, Q: std_logic_vector(3 downto 0); > > signal count, clear: std_logic; > > > begin > > > -- behavior describe the counter > > process(clk, count, clear) > > begin > > if (clear = '0') then > > Pre_Q <= Pre_Q - Pre_Q; > > elsif (clk='1' and clk'event) then > > if (count = '1') then > > Pre_Q <= Pre_Q + 1; > > end if; > > end if; > > Q <= Pre_Q; > > end process; > > > -- state register > > > process(clk,reset) > > begin > > if(reset='0') then > > state_reg <= a; > > elsif (clk'event and clk='1') then > > state_reg <= state_next; > > end if; > > end process; > > > -- next state logic > > > process(state_reg,Q,sa,sb) > > begin > > > case state_reg is > > when a => > > if(sa = '1' and sb = '0')then > > state_next <= a; > > elsif (sa = '0' and sb = '1') then > > count <= '1'; > > if(Q = "0110") then > > state_next <= b; > > end if; > > end if; > > > when b => > > > if(Q = "0111") then > > state_next <= c; > > count <= '0'; > > elsif(sa = '1') then > > state_next <= b; > > end if; > > > when c => > > if(sa = '0' and sb = '1') then > > state_next <= c; > > elsif (sa = '1' and sb ='0') then > > clear <= '0'; > > count <= '1'; > > if(Q = "0110") then > > state_next <= d; > > > end if; > > end if; > > > when d => > > > if(Q = "0111") then > > state_next <= a; > > count <= '0'; > > elsif(sb = '1') then > > state_next <= d; > > end if; > > end case; > > end process; > > > process (state_reg) > > begin > > Ga <= '1'; Ya <= '0'; Ra <= '0'; > > Gb <= '0'; Yb <= '0'; Rb <= '1'; > > > case state_reg is > > when a => > > when b => > > Ga <= '0'; > > Ya <= '1'; > > > when c => > > Ya <= '0'; > > Ra <= '1'; > > Gb <= '1'; > > > when d => > > Gb <= '0'; > > Yb <= '1'; > > > end case; > > > end process; > > > end Behavioral; > > ----------------------------------------------------------------------------------------------------------------------------------------------------------Thanx for the solution. I was also thinking about making counter integer. Can you please elaborate on that? will it be like adding for loop till count reach to desired value and then perform the transition? thanx again
Reply by ●December 1, 20072007-12-01
On Nov 30, 6:16 pm, "Symon" <symon_bre...@hotmail.com> wrote:> "tang" <tarangpatel2elect...@gmail.com> wrote in message > > news:48da85be-c67e-479c-8b6c-3824f5e98ee9@d61g2000hsa.googlegroups.com...> hey guys i hope u can help me out... i want to design a simple traffic > > light controller according to the 4 states shown in the code below. my > > only problem is that my signal state_reg is not changing form one > > state to another. this is because the counter i included in the the > > code as a process is not working. green to yellow time wait is 30 sec > > and yellow to red is 5 sec. my clock period will be 5 sec. so can > > anyone help me out > > Hey tang, > You should try comp.lang.vhdl . There are a bunch of blokes over there who > _really_ know how sensitivity lists work. Ask for Mike xor Jonathan orif > Jim. They're among the best at homework. Tell them I sent you. > HTH., Syms. > p.s. These days, 'traffic light vhdl' is at 159000 Google hits. Adding > lumberjack to the search gets you down to a more sensible 39. Only two worse > than adding omg ponies. (Thanks to Ben J. for that insight!) Be sure to turn > off 'safe search'.thanx for the reply...
Reply by ●December 1, 20072007-12-01
Symon wrote:> p.s. These days, 'traffic light vhdl' is at 159000 Google hits. Adding > lumberjack to the search gets you down to a more sensible 39.farm_traffic takes it down to one. http://groups.google.com/groups/search?q=farm_traffic -- Mike Treseler
Reply by ●December 1, 20072007-12-01
On Sat, 01 Dec 2007 11:33:23 -0800, Mike Treseler wrote:>farm_traffic takes it down to one. >http://groups.google.com/groups/search?q=farm_trafficSorry Mike, it's two now - and this post will make it three :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
Reply by ●December 1, 20072007-12-01
"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message news:8ln3l3pdrhgq93k3qj5fj2u16ka5k6a7iq@4ax.com...> On Sat, 01 Dec 2007 11:33:23 -0800, Mike Treseler wrote: > >>farm_traffic takes it down to one. >>http://groups.google.com/groups/search?q=farm_traffic > > Sorry Mike, it's two now - and this post will make it three :-) > -- > Jonathan Bromley, Consultant >My gosh, you're right....it just keeps a growin, will it never end???? Can get it back down to 1 though by filtering out anything with the following words mike treseler wrote jonathan bromley http://groups.google.com/groups?as_q=farm_traffic&num=10&scoring=r&as_epq=&as_oq=&as_eq=Mike+Treseler+wrote+Jonathan+Bromley&as_ugroup=&as_usubject=&as_uauthors=&lr=&as_drrb=q&as_qdr=&as_mind=1&as_minm=1&as_miny=1981&as_maxd=1&as_maxm=12&as_maxy=2007&safe=off KJ
