Virtex5: LVCMOS33 and LVDS_25 inputs (with DIFF_TERM) in same bank?

To avoid going to a larger package, I want to mix LVDS_25 inputs with
LVCMOS33 in the same I/O bank, with VCCO = 3.3V.  I would also like to
use the DIFF_TERM attribute on the LVDS inputs, to avoid external
resistors, for better signal integrity and PCB routing.  But
apparently the LVDS differential termination uses VCCO, so it is
required to be 2.5V with this attribute.  Do I have any options to
achieve what I want, or is there just no way.

TIA,
Barry Brown

On Dec 3, 8:16 am, Barry <barry...@gmail.com> wrote:
> To avoid going to a larger package, I want to mix LVDS_25 inputs with
> LVCMOS33 in the same I/O bank, with VCCO = 3.3V.  I would also like to
> use the DIFF_TERM attribute on the LVDS inputs, to avoid external
> resistors, for better signal integrity and PCB routing.  But
> apparently the LVDS differential termination uses VCCO, so it is
> required to be 2.5V with this attribute.  Do I have any options to
> achieve what I want, or is there just no way.
>
> TIA,
> Barry Brown

The DIFF_TERM functionality is powered by 2.5V.  Just add the external
resistors and you can mix input I/Os to your heart's content.

Barry wrote:
> To avoid going to a larger package, I want to mix LVDS_25 inputs with
> LVCMOS33 in the same I/O bank, with VCCO = 3.3V.  I would also like to
> use the DIFF_TERM attribute on the LVDS inputs, to avoid external
> resistors, for better signal integrity and PCB routing.  But
> apparently the LVDS differential termination uses VCCO, so it is
> required to be 2.5V with this attribute.  Do I have any options to
> achieve what I want, or is there just no way.
You can use the internal termination even if VCCO=3.3V, but then the
termination value is not 100 Ohms. What the value really is is not
specified, since it's not recommended to be used this way, but you can
do it without "hurting" the FPGA or anything. I have used this
configuration on a Virtex4-device, worked without any problems (but the
LVDS signal wasn't very fast and the connections short).

Another problem is that since ISE9.1 the tools won't allow you to put
LVDS-Inputs in the same bank as LVTTL-outputs; par then just quits with
a fatal error message (tool versions before that didn't even issue a
warning). If you want to override that you have to set the environment
variable "PL_NO_SIO_DRC" to 1.

The best solution is probably to provide external termination resistors,
like John said. If you use 0402 resistors you can usually put them on
the opposite side of the PCB right between or even on top of the vias
that come down from the FPGA balls.

HTH,
Sean

-- 
My email address is only valid until the end of the month.
Try figuring out what the address is going to be after that...

"Barry" <barry374@gmail.com> wrote in message 
news:7a60bfbf-0bfc-4599-9f57-99b892c23a03@n20g2000hsh.googlegroups.com...
> To avoid going to a larger package, I want to mix LVDS_25 inputs with
> LVCMOS33 in the same I/O bank, with VCCO = 3.3V.  I would also like to
> use the DIFF_TERM attribute on the LVDS inputs, to avoid external
> resistors, for better signal integrity and PCB routing.  But
> apparently the LVDS differential termination uses VCCO, so it is
> required to be 2.5V with this attribute.  Do I have any options to
> achieve what I want, or is there just no way.
>

Hi Barry,
What's the rise time of the LVDS signals you want to terminate? Are they 
driven from a source that has 'proper' LVDS source termination?
http://pdfserv.maxim-ic.com/en/an/hfan10v2.pdf fig.6 shows source 
termination.
Syms. 

On Dec 3, 9:35 am, "Symon" <symon_bre...@hotmail.com> wrote:
> "Barry" <barry...@gmail.com> wrote in message
>
> news:7a60bfbf-0bfc-4599-9f57-99b892c23a03@n20g2000hsh.googlegroups.com...
>
> > To avoid going to a larger package, I want to mix LVDS_25 inputs with
> > LVCMOS33 in the same I/O bank, with VCCO = 3.3V.  I would also like to
> > use the DIFF_TERM attribute on the LVDS inputs, to avoid external
> > resistors, for better signal integrity and PCB routing.  But
> > apparently the LVDS differential termination uses VCCO, so it is
> > required to be 2.5V with this attribute.  Do I have any options to
> > achieve what I want, or is there just no way.
>
> Hi Barry,
> What's the rise time of the LVDS signals you want to terminate? Are they
> driven from a source that has 'proper' LVDS source termination?http://pdfserv.maxim-ic.com/en/an/hfan10v2.pdffig.6 shows source
> termination.
> Syms.

The driver is a Texas Instruments ADS6244 ADC.  Rise time is spec'd
between 50 and 200 psec (from -100mV to +100mV), and my data rate will
be 800Mbps.  The device's LVDS drivers have a configurable internal
termination, which I can set to 100 ohm differential if I desire, at
the expense of a little more power dissipation.

On Dec 3, 9:13 am, Sean Durkin <news_de...@durkin.de> wrote:
> Barry wrote:
> > To avoid going to a larger package, I want to mix LVDS_25 inputs with
> > LVCMOS33 in the same I/O bank, with VCCO = 3.3V.  I would also like to
> > use the DIFF_TERM attribute on the LVDS inputs, to avoid external
> > resistors, for better signal integrity and PCB routing.  But
> > apparently the LVDS differential termination uses VCCO, so it is
> > required to be 2.5V with this attribute.  Do I have any options to
> > achieve what I want, or is there just no way.
>
> You can use the internal termination even if VCCO=3.3V, but then the
> termination value is not 100 Ohms. What the value really is is not
> specified, since it's not recommended to be used this way, but you can
> do it without "hurting" the FPGA or anything. I have used this
> configuration on a Virtex4-device, worked without any problems (but the
> LVDS signal wasn't very fast and the connections short).
>
> Another problem is that since ISE9.1 the tools won't allow you to put
> LVDS-Inputs in the same bank as LVTTL-outputs; par then just quits with
> a fatal error message (tool versions before that didn't even issue a
> warning). If you want to override that you have to set the environment
> variable "PL_NO_SIO_DRC" to 1.
>
> The best solution is probably to provide external termination resistors,
> like John said. If you use 0402 resistors you can usually put them on
> the opposite side of the PCB right between or even on top of the vias
> that come down from the FPGA balls.
>
> HTH,
> Sean
>
> --
> My email address is only valid until the end of the month.
> Try figuring out what the address is going to be after that...

Thanks, Sean.  I will probably have to use external resistors then.
And thanks for the tip on the environment variable.

"Barry" <barry374@gmail.com> wrote in message 
news:c800e4d7-0d73-4590-afe5-1581e9025327@d4g2000prg.googlegroups.com...

>
> The driver is a Texas Instruments ADS6244 ADC.  Rise time is spec'd
> between 50 and 200 psec (from -100mV to +100mV), and my data rate will
> be 800Mbps.  The device's LVDS drivers have a configurable internal
> termination, which I can set to 100 ohm differential if I desire, at
> the expense of a little more power dissipation.
>
Hi Barry,
OK, so the signals are fast! But, because you can set the source 
termination, the design will almost certainly work even with the inaccurate 
LVDS termination in the FPGA caused by the out of spec. Vcco you're 
considering. Hell, the FPGA's ~10pF Cpin already screws with the termination 
enough. I suggest you try simulating to confirm the circuit's operation, 
however you decide to proceed.
HTH., Syms.