What to look for when synthesising verilog code originally written for ASIC to FPGA?

Regarding to necessary changes to verilog code, am I missing
something,
1. caches and memories, replacing using FPGA block rams.
2. clock gating to clock enable
3. change latches to registers
Anything else?

On Dec 8, 8:27 am, wei.wang.can...@googlemail.com wrote:
> Regarding to necessary changes to verilog code, am I missing
> something,
> 1. caches and memories, replacing using FPGA block rams.
> 2. clock gating to clock enable
> 3. change latches to registers
> Anything else?

That's a very broad question. What you need to do during the ASIC-
>FPGA conversion is very dependent on the architecture of the target
FPGA. For example, many (but not all) modern FPGAs include multiplier
or MAC macros and fast adder chains. If your ASIC used multiply or add
operations they may have been coded at the gate level which is
wasteful if your FPGA has these built-in. In this case you'll want to
abstract the arithmetic functions to allow inference of the native
FPGA resources, or instantiate the primitives in your source code.

EB