Hi All , I am new to FPGA development and have learned VHDL using text books. NOW! that doesn't teach practical aspects! I am extremely confused with the following discovery - I am using Spartan 3 400k device and it has 16 block rams. I have configured a microblaze system to use block ram as follows - 1) Local memory - 16 Kbytes 2) OPB Block Ram 1 - 8Kbytes 3) OPB Block Ran 2 - 8Kbytes That means that it has used up all the block Rams. Now the confusing part - I have designed an IP which consumes 15 Block Rams , and when I include the IP in my microblaze system , the bitstream gets generated! The synthesis report shows that my IP is using up 15 Block Rams and that microblaze momories are using up 16 Block Rams! That means that the system is using up 31 Block Rams! How is that Possilbe? Any help would be greatly appreciated. BR Rate
Newbee Microblaze system BRAM utlization confusion
Started by ●December 12, 2007
Reply by ●December 13, 20072007-12-13
Hi, Can you show the system.mhs file and the system_map.mrp contents? You can't have 31 BRAMs in a device with 16 BRAMs. There is no extra magic inside the FPGA, just the usual magic. G�ran "ratemonotonic" <niladri1979@gmail.com> wrote in message news:2a8577bd-197c-4d03-8bfc-3f37ed87cfef@e25g2000prg.googlegroups.com...> Hi All , > > I am new to FPGA development and have learned VHDL using text books. > NOW! that doesn't teach practical aspects! > I am extremely confused with the following discovery - > > I am using Spartan 3 400k device and it has 16 block rams. > I have configured a microblaze system to use block ram as follows - > > 1) Local memory - 16 Kbytes > 2) OPB Block Ram 1 - 8Kbytes > 3) OPB Block Ran 2 - 8Kbytes > > That means that it has used up all the block Rams. > > Now the confusing part - I have designed an IP which consumes 15 > Block Rams , and when I include the IP in my microblaze system , the > bitstream gets generated! The synthesis report shows that my IP is > using up 15 Block Rams and that microblaze momories are using up 16 > Block Rams! That means that the system is using up 31 Block Rams! > > How is that Possilbe? > > Any help would be greatly appreciated. > > BR > Rate
Reply by ●December 13, 20072007-12-13
On Wed, 12 Dec 2007 07:49:18 -0800 (PST), ratemonotonic <niladri1979@gmail.com> wrote:>Hi All , > >I am new to FPGA development and have learned VHDL using text books. >NOW! that doesn't teach practical aspects! >I am extremely confused with the following discovery - > >Now the confusing part - I have designed an IP which consumes 15 >Block Rams , and when I include the IP in my microblaze system , the >bitstream gets generated! The synthesis report shows that my IP is >using up 15 Block Rams and that microblaze momories are using up 16 >Block Rams! That means that the system is using up 31 Block Rams! > >How is that Possilbe?The final synthesis report probably shows about 190% of the BRAM resources are used. The synthesis output is valid - BUT - will not pass through the implementation tools until you either: redesign to use fewer resources, or: target a bigger FPGA. If you don't want to re-design, low cost boards are available with the Spartan-3 1500. Here's one... http://www.enterpoint.co.uk/moelbryn/raggedstone1.html - Brian
Reply by ●December 13, 20072007-12-13
On Dec 13, 12:23 pm, Brian Drummond <brian_drumm...@btconnect.com> wrote:> On Wed, 12 Dec 2007 07:49:18 -0800 (PST), ratemonotonic > > <niladri1...@gmail.com> wrote: > >Hi All , > > >I am new to FPGA development and have learned VHDL using text books. > >NOW! that doesn't teach practical aspects! > >I am extremely confused with the following discovery - > > >Now the confusing part - I have designed an IP which consumes 15 > >Block Rams , and when I include the IP in my microblaze system , the > >bitstream gets generated! The synthesis report shows that my IP is > >using up 15 Block Rams and that microblaze momories are using up 16 > >Block Rams! That means that the system is using up 31 Block Rams! > > >How is that Possilbe? > > The final synthesis report probably shows about 190% of the BRAM > resources are used. > > The synthesis output is valid - BUT - will not pass through the > implementation tools until you either: redesign to use fewer resources, > or: target a bigger FPGA. > > If you don't want to re-design, low cost boards are available with the > Spartan-3 1500. Here's one... > > http://www.enterpoint.co.uk/moelbryn/raggedstone1.html > > - Brianyes it is confusing because I am able to burn the logic and step through the C code! The system.mhh is as follows - # ############################################################################## # Created by Base System Builder Wizard for Xilinx EDK 9.2 Build EDK_Jm.16 # Tue Dec 11 11:23:35 2007 # Target Board: Memec Spartan-3 3S400LC Development Board Rev 2 # Family: spartan3 # Device: XC3S400 # Package: PQ208 # Speed Grade: -4 # Processor: microblaze_0 # System clock frequency: 50.000000 MHz # On Chip Memory : 16 KB # ############################################################################## PARAMETER VERSION = 2.1.0 PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = I PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = O PORT fpga_0_DIP_Switches_4Bit_GPIO_in_pin = fpga_0_DIP_Switches_4Bit_GPIO_in, DIR = I, VEC = [0:3] PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST BEGIN microblaze PARAMETER HW_VER = 7.00.a PARAMETER INSTANCE = microblaze_0 PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_AREA_OPTIMIZED = 1 PARAMETER C_FSL_LINKS = 1 PARAMETER C_FAMILY = spartan3 PARAMETER C_INSTANCE = microblaze_0 BUS_INTERFACE DPLB = mb_plb BUS_INTERFACE IPLB = mb_plb BUS_INTERFACE DEBUG = microblaze_0_dbg BUS_INTERFACE SFSL0 = modem_fsl_wrapper_0_to_microblaze_0_0 BUS_INTERFACE DLMB = dlmb BUS_INTERFACE ILMB = ilmb BUS_INTERFACE MFSL0 = microblaze_0_to_modem_fsl_wrapper_0_0 PORT RESET = mb_reset PORT INTERRUPT = microblaze_0_INTERRUPT END BEGIN plb_v46 PARAMETER INSTANCE = mb_plb PARAMETER HW_VER = 1.00.a PORT PLB_Clk = sys_clk_s PORT SYS_Rst = sys_bus_reset END BEGIN lmb_v10 PARAMETER INSTANCE = ilmb PARAMETER HW_VER = 1.00.a PORT LMB_Clk = sys_clk_s PORT SYS_Rst = sys_bus_reset END BEGIN lmb_v10 PARAMETER INSTANCE = dlmb PARAMETER HW_VER = 1.00.a PORT LMB_Clk = sys_clk_s PORT SYS_Rst = sys_bus_reset END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = dlmb_cntlr PARAMETER HW_VER = 2.10.a PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00007FFF BUS_INTERFACE SLMB = dlmb BUS_INTERFACE BRAM_PORT = dlmb_cntlr_BRAM_PORT END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = ilmb_cntlr PARAMETER HW_VER = 2.10.a PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00007FFF BUS_INTERFACE SLMB = ilmb BUS_INTERFACE BRAM_PORT = ilmb_cntlr_BRAM_PORT END BEGIN bram_block PARAMETER INSTANCE = lmb_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTB = dlmb_cntlr_BRAM_PORT BUS_INTERFACE PORTA = ilmb_cntlr_BRAM_PORT END BEGIN xps_uartlite PARAMETER INSTANCE = RS232 PARAMETER HW_VER = 1.00.a PARAMETER C_BAUDRATE = 9600 PARAMETER C_DATA_BITS = 8 PARAMETER C_ODD_PARITY = 0 PARAMETER C_USE_PARITY = 0 PARAMETER C_SPLB_CLK_FREQ_HZ = 50000000 PARAMETER C_BASEADDR = 0x83c12000 PARAMETER C_HIGHADDR = 0x83c121ff BUS_INTERFACE SPLB = mb_plb PORT RX = fpga_0_RS232_RX PORT TX = fpga_0_RS232_TX END BEGIN xps_gpio PARAMETER INSTANCE = DIP_Switches_4Bit PARAMETER HW_VER = 1.00.a PARAMETER C_GPIO_WIDTH = 4 PARAMETER C_IS_DUAL = 0 PARAMETER C_ALL_INPUTS = 1 PARAMETER C_IS_BIDIR = 0 PARAMETER C_BASEADDR = 0x81400000 PARAMETER C_HIGHADDR = 0x8140ffff BUS_INTERFACE SPLB = mb_plb PORT GPIO_in = fpga_0_DIP_Switches_4Bit_GPIO_in END BEGIN xps_timer PARAMETER INSTANCE = timer_counter PARAMETER HW_VER = 1.00.a PARAMETER C_ONE_TIMER_ONLY = 1 PARAMETER C_BASEADDR = 0x83c00000 PARAMETER C_HIGHADDR = 0x83c0ffff BUS_INTERFACE SPLB = mb_plb PORT Interrupt = timer1 PORT CaptureTrig0 = net_gnd END BEGIN clock_generator PARAMETER INSTANCE = clock_generator_0 PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 1 PARAMETER C_CLKIN_FREQ = 50000000 PARAMETER C_CLKOUT0_FREQ = 50000000 PARAMETER C_CLKOUT0_PHASE = 0 PARAMETER C_CLKOUT0_GROUP = NONE PORT CLKOUT0 = sys_clk_s PORT CLKIN = dcm_clk_s PORT LOCKED = Dcm_all_locked PORT RST = net_gnd END BEGIN mdm PARAMETER INSTANCE = debug_module PARAMETER HW_VER = 1.00.a PARAMETER C_MB_DBG_PORTS = 1 PARAMETER C_USE_UART = 1 PARAMETER C_UART_WIDTH = 8 PARAMETER C_BASEADDR = 0x84400000 PARAMETER C_HIGHADDR = 0x8440ffff BUS_INTERFACE SPLB = mb_plb BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg PORT Debug_SYS_Rst = Debug_SYS_Rst END BEGIN proc_sys_reset PARAMETER INSTANCE = proc_sys_reset_0 PARAMETER HW_VER = 2.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT Slowest_sync_clk = sys_clk_s PORT Dcm_locked = Dcm_all_locked PORT Ext_Reset_In = sys_rst_s PORT MB_Reset = mb_reset PORT Bus_Struct_Reset = sys_bus_reset PORT MB_Debug_Sys_Rst = Debug_SYS_Rst END BEGIN fsl_v20 PARAMETER INSTANCE = modem_fsl_wrapper_0_to_microblaze_0_0 PARAMETER HW_VER = 2.11.a PORT FSL_Clk = sys_clk_s PORT SYS_Rst = net_gnd END BEGIN modem_fsl_wrapper PARAMETER INSTANCE = modem_fsl_wrapper_0 BUS_INTERFACE MFSL = modem_fsl_wrapper_0_to_microblaze_0_0 BUS_INTERFACE SFSL = microblaze_0_to_modem_fsl_wrapper_0_0 PORT FSL_Clk = sys_clk_s END BEGIN fsl_v20 PARAMETER INSTANCE = microblaze_0_to_modem_fsl_wrapper_0_0 PARAMETER HW_VER = 2.11.a PORT FSL_Clk = sys_clk_s PORT SYS_Rst = net_gnd END BEGIN xps_intc PARAMETER INSTANCE = xps_intc_0 PARAMETER HW_VER = 1.00.a PARAMETER C_BASEADDR = 0x83c14000 PARAMETER C_HIGHADDR = 0x83c141ff BUS_INTERFACE SPLB = mb_plb PORT Irq = microblaze_0_INTERRUPT PORT Intr = timer1 END BEGIN util_vector_logic PARAMETER INSTANCE = util_vector_logic_0 PARAMETER HW_VER = 1.00.a END The guilty modules are - 1)modem_fsl_wrapper whose device utilisation summary is - Selected Device : 3s400pq208-4 Number of Slices: 665 out of 3584 18% Number of Slice Flip Flops: 841 out of 7168 11% Number of 4 input LUTs: 995 out of 7168 13% Number used as logic: 923 Number used as Shift registers: 72 Number of IOs: 140 Number of bonded IOBs: 0 out of 141 0% Number of BRAMs: 15 out of 16 93% Number of MULT18X18s: 16 out of 16 100% Number of GCLKs: 6 out of 8 75% 2) Local BRAM - device utilisatioin - Device utilization summary: --------------------------- Selected Device : 3s400pq208-4 Number of Slices: 0 out of 3584 0% Number of IOs: 206 Number of bonded IOBs: 0 out of 141 0% Number of BRAMs: 16 out of 16 100% Thanks for the guidance ! BR Rate
Reply by ●December 13, 20072007-12-13
On Dec 13, 12:23 pm, Brian Drummond <brian_drumm...@btconnect.com> wrote:> On Wed, 12 Dec 2007 07:49:18 -0800 (PST), ratemonotonic > > <niladri1...@gmail.com> wrote: > >Hi All , > > >I am new to FPGA development and have learned VHDL using text books. > >NOW! that doesn't teach practical aspects! > >I am extremely confused with the following discovery - > > >Now the confusing part - I have designed an IP which consumes 15 > >Block Rams , and when I include the IP in my microblaze system , the > >bitstream gets generated! The synthesis report shows that my IP is > >using up 15 Block Rams and that microblaze momories are using up 16 > >Block Rams! That means that the system is using up 31 Block Rams! > > >How is that Possilbe? > > The final synthesis report probably shows about 190% of the BRAM > resources are used. > > The synthesis output is valid - BUT - will not pass through the > implementation tools until you either: redesign to use fewer resources, > or: target a bigger FPGA. > > If you don't want to re-design, low cost boards are available with the > Spartan-3 1500. Here's one... > > http://www.enterpoint.co.uk/moelbryn/raggedstone1.html > > - BrianOn Dec 13, 12:23 pm, Brian Drummond <brian_drumm...@btconnect.com> wrote:> On Wed, 12 Dec 2007 07:49:18 -0800 (PST), ratemonotonic > > <niladri1...@gmail.com> wrote: > >Hi All , > > >I am new to FPGA development and have learned VHDL using text books. > >NOW! that doesn't teach practical aspects! > >I am extremely confused with the following discovery - > > >Now the confusing part - I have designed an IP which consumes 15 > >Block Rams , and when I include the IP in my microblaze system , the > >bitstream gets generated! The synthesis report shows that my IP is > >using up 15 Block Rams and that microblaze momories are using up 16 > >Block Rams! That means that the system is using up 31 Block Rams! > > >How is that Possilbe? > > The final synthesis report probably shows about 190% of the BRAM > resources are used. > > The synthesis output is valid - BUT - will not pass through the > implementation tools until you either: redesign to use fewer resources, > or: target a bigger FPGA. > > If you don't want to re-design, low cost boards are available with the > Spartan-3 1500. Here's one... > > http://www.enterpoint.co.uk/moelbryn/raggedstone1.html > > - Brianyes it is confusing because I am able to burn the logic and step through the C code! The system.mhh is as follows - # ############################################################################## # Created by Base System Builder Wizard for Xilinx EDK 9.2 Build EDK_Jm.16 # Tue Dec 11 11:23:35 2007 # Target Board: Memec Spartan-3 3S400LC Development Board Rev 2 # Family: spartan3 # Device: XC3S400 # Package: PQ208 # Speed Grade: -4 # Processor: microblaze_0 # System clock frequency: 50.000000 MHz # On Chip Memory : 16 KB # ############################################################################## PARAMETER VERSION = 2.1.0 PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = I PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = O PORT fpga_0_DIP_Switches_4Bit_GPIO_in_pin = fpga_0_DIP_Switches_4Bit_GPIO_in, DIR = I, VEC = [0:3] PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST BEGIN microblaze PARAMETER HW_VER = 7.00.a PARAMETER INSTANCE = microblaze_0 PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_AREA_OPTIMIZED = 1 PARAMETER C_FSL_LINKS = 1 PARAMETER C_FAMILY = spartan3 PARAMETER C_INSTANCE = microblaze_0 BUS_INTERFACE DPLB = mb_plb BUS_INTERFACE IPLB = mb_plb BUS_INTERFACE DEBUG = microblaze_0_dbg BUS_INTERFACE SFSL0 = modem_fsl_wrapper_0_to_microblaze_0_0 BUS_INTERFACE DLMB = dlmb BUS_INTERFACE ILMB = ilmb BUS_INTERFACE MFSL0 = microblaze_0_to_modem_fsl_wrapper_0_0 PORT RESET = mb_reset PORT INTERRUPT = microblaze_0_INTERRUPT END BEGIN plb_v46 PARAMETER INSTANCE = mb_plb PARAMETER HW_VER = 1.00.a PORT PLB_Clk = sys_clk_s PORT SYS_Rst = sys_bus_reset END BEGIN lmb_v10 PARAMETER INSTANCE = ilmb PARAMETER HW_VER = 1.00.a PORT LMB_Clk = sys_clk_s PORT SYS_Rst = sys_bus_reset END BEGIN lmb_v10 PARAMETER INSTANCE = dlmb PARAMETER HW_VER = 1.00.a PORT LMB_Clk = sys_clk_s PORT SYS_Rst = sys_bus_reset END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = dlmb_cntlr PARAMETER HW_VER = 2.10.a PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00007FFF BUS_INTERFACE SLMB = dlmb BUS_INTERFACE BRAM_PORT = dlmb_cntlr_BRAM_PORT END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = ilmb_cntlr PARAMETER HW_VER = 2.10.a PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00007FFF BUS_INTERFACE SLMB = ilmb BUS_INTERFACE BRAM_PORT = ilmb_cntlr_BRAM_PORT END BEGIN bram_block PARAMETER INSTANCE = lmb_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTB = dlmb_cntlr_BRAM_PORT BUS_INTERFACE PORTA = ilmb_cntlr_BRAM_PORT END BEGIN xps_uartlite PARAMETER INSTANCE = RS232 PARAMETER HW_VER = 1.00.a PARAMETER C_BAUDRATE = 9600 PARAMETER C_DATA_BITS = 8 PARAMETER C_ODD_PARITY = 0 PARAMETER C_USE_PARITY = 0 PARAMETER C_SPLB_CLK_FREQ_HZ = 50000000 PARAMETER C_BASEADDR = 0x83c12000 PARAMETER C_HIGHADDR = 0x83c121ff BUS_INTERFACE SPLB = mb_plb PORT RX = fpga_0_RS232_RX PORT TX = fpga_0_RS232_TX END BEGIN xps_gpio PARAMETER INSTANCE = DIP_Switches_4Bit PARAMETER HW_VER = 1.00.a PARAMETER C_GPIO_WIDTH = 4 PARAMETER C_IS_DUAL = 0 PARAMETER C_ALL_INPUTS = 1 PARAMETER C_IS_BIDIR = 0 PARAMETER C_BASEADDR = 0x81400000 PARAMETER C_HIGHADDR = 0x8140ffff BUS_INTERFACE SPLB = mb_plb PORT GPIO_in = fpga_0_DIP_Switches_4Bit_GPIO_in END BEGIN xps_timer PARAMETER INSTANCE = timer_counter PARAMETER HW_VER = 1.00.a PARAMETER C_ONE_TIMER_ONLY = 1 PARAMETER C_BASEADDR = 0x83c00000 PARAMETER C_HIGHADDR = 0x83c0ffff BUS_INTERFACE SPLB = mb_plb PORT Interrupt = timer1 PORT CaptureTrig0 = net_gnd END BEGIN clock_generator PARAMETER INSTANCE = clock_generator_0 PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 1 PARAMETER C_CLKIN_FREQ = 50000000 PARAMETER C_CLKOUT0_FREQ = 50000000 PARAMETER C_CLKOUT0_PHASE = 0 PARAMETER C_CLKOUT0_GROUP = NONE PORT CLKOUT0 = sys_clk_s PORT CLKIN = dcm_clk_s PORT LOCKED = Dcm_all_locked PORT RST = net_gnd END BEGIN mdm PARAMETER INSTANCE = debug_module PARAMETER HW_VER = 1.00.a PARAMETER C_MB_DBG_PORTS = 1 PARAMETER C_USE_UART = 1 PARAMETER C_UART_WIDTH = 8 PARAMETER C_BASEADDR = 0x84400000 PARAMETER C_HIGHADDR = 0x8440ffff BUS_INTERFACE SPLB = mb_plb BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg PORT Debug_SYS_Rst = Debug_SYS_Rst END BEGIN proc_sys_reset PARAMETER INSTANCE = proc_sys_reset_0 PARAMETER HW_VER = 2.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT Slowest_sync_clk = sys_clk_s PORT Dcm_locked = Dcm_all_locked PORT Ext_Reset_In = sys_rst_s PORT MB_Reset = mb_reset PORT Bus_Struct_Reset = sys_bus_reset PORT MB_Debug_Sys_Rst = Debug_SYS_Rst END BEGIN fsl_v20 PARAMETER INSTANCE = modem_fsl_wrapper_0_to_microblaze_0_0 PARAMETER HW_VER = 2.11.a PORT FSL_Clk = sys_clk_s PORT SYS_Rst = net_gnd END BEGIN modem_fsl_wrapper PARAMETER INSTANCE = modem_fsl_wrapper_0 BUS_INTERFACE MFSL = modem_fsl_wrapper_0_to_microblaze_0_0 BUS_INTERFACE SFSL = microblaze_0_to_modem_fsl_wrapper_0_0 PORT FSL_Clk = sys_clk_s END BEGIN fsl_v20 PARAMETER INSTANCE = microblaze_0_to_modem_fsl_wrapper_0_0 PARAMETER HW_VER = 2.11.a PORT FSL_Clk = sys_clk_s PORT SYS_Rst = net_gnd END BEGIN xps_intc PARAMETER INSTANCE = xps_intc_0 PARAMETER HW_VER = 1.00.a PARAMETER C_BASEADDR = 0x83c14000 PARAMETER C_HIGHADDR = 0x83c141ff BUS_INTERFACE SPLB = mb_plb PORT Irq = microblaze_0_INTERRUPT PORT Intr = timer1 END BEGIN util_vector_logic PARAMETER INSTANCE = util_vector_logic_0 PARAMETER HW_VER = 1.00.a END The guilty modules are - 1)modem_fsl_wrapper whose device utilisation summary is - Selected Device : 3s400pq208-4 Number of Slices: 665 out of 3584 18% Number of Slice Flip Flops: 841 out of 7168 11% Number of 4 input LUTs: 995 out of 7168 13% Number used as logic: 923 Number used as Shift registers: 72 Number of IOs: 140 Number of bonded IOBs: 0 out of 141 0% Number of BRAMs: 15 out of 16 93% Number of MULT18X18s: 16 out of 16 100% Number of GCLKs: 6 out of 8 75% 2) Local BRAM - device utilisatioin - Device utilization summary: --------------------------- Selected Device : 3s400pq208-4 Number of Slices: 0 out of 3584 0% Number of IOs: 206 Number of bonded IOBs: 0 out of 141 0% Number of BRAMs: 16 out of 16 100% Thanks for the guidance ! BR Rate
Reply by ●December 13, 20072007-12-13
On Dec 13, 12:23 pm, Brian Drummond <brian_drumm...@btconnect.com> wrote:> On Wed, 12 Dec 2007 07:49:18 -0800 (PST), ratemonotonic > > <niladri1...@gmail.com> wrote: > >Hi All , > > >I am new to FPGA development and have learned VHDL using text books. > >NOW! that doesn't teach practical aspects! > >I am extremely confused with the following discovery - > > >Now the confusing part - I have designed an IP which consumes 15 > >Block Rams , and when I include the IP in my microblaze system , the > >bitstream gets generated! The synthesis report shows that my IP is > >using up 15 Block Rams and that microblaze momories are using up 16 > >Block Rams! That means that the system is using up 31 Block Rams! > > >How is that Possilbe? > > The final synthesis report probably shows about 190% of the BRAM > resources are used. > > The synthesis output is valid - BUT - will not pass through the > implementation tools until you either: redesign to use fewer resources, > or: target a bigger FPGA. > > If you don't want to re-design, low cost boards are available with the > Spartan-3 1500. Here's one... > > http://www.enterpoint.co.uk/moelbryn/raggedstone1.html > > - Brianspartan 3 400 has 56Kbit distributed RAM is it possible that the synthesizer is using then as block RAMs as well? BR Rate
Reply by ●December 13, 20072007-12-13
On Dec 13, 10:16 am, ratemonotonic <niladri1...@gmail.com> wrote:> On Dec 13, 12:23 pm, Brian Drummond <brian_drumm...@btconnect.com> > wrote: > > > > > On Wed, 12 Dec 2007 07:49:18 -0800 (PST), ratemonotonic > > > <niladri1...@gmail.com> wrote: > > >Hi All , > > > >I am new to FPGA development and have learned VHDL using text books. > > >NOW! that doesn't teach practical aspects! > > >I am extremely confused with the following discovery - > > > >Now the confusing part - I have designed an IP which consumes 15 > > >Block Rams , and when I include the IP in my microblaze system , the > > >bitstream gets generated! The synthesis report shows that my IP is > > >using up 15 Block Rams and that microblaze momories are using up 16 > > >Block Rams! That means that the system is using up 31 Block Rams! > > > >How is that Possilbe? > > > The final synthesis report probably shows about 190% of the BRAM > > resources are used. > > > The synthesis output is valid - BUT - will not pass through the > > implementation tools until you either: redesign to use fewer resources, > > or: target a bigger FPGA. > > > If you don't want to re-design, low cost boards are available with the > > Spartan-3 1500. Here's one... > > >http://www.enterpoint.co.uk/moelbryn/raggedstone1.html > > > - Brian > > yes it is confusing because I am able to burn the logic and step > through the C code! > The system.mhh is as follows - >Look at the map report and see what utilization it reports. Many optimizations are performed in the map phase, including removing unconnected/unused resources. It may be that something is not connected the way you meant it to be, and map is removing it. This can happen during development if not all of your signals are connected yet. If that is the case, it may not help your situation of wanting to use more BRAMS than are in the device, but it explains why your design made it through place and route. Regards, John McCaskill
Reply by ●December 13, 20072007-12-13
Göran Bilski wrote:> There is no extra magic inside the FPGA, just the usual magic.I'll have to remember that one! :-)
Reply by ●December 14, 20072007-12-14
This is a multi-part message in MIME format. ------=_NextPart_000_0041_01C83E32.04930510 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hi, From your email I found this. It looks everything has been trimmed away since you are using 0% slices = and 0 pads. If you look at the system_map.mrp file, there is a section on what has = been trimmed away. That could give you a hint what is causing this. You might also add the = option "-detail" to the map tool. G=F6ran Device utilization summary: --------------------------- Selected Device : 3s400pq208-4 Number of Slices: 0 out of 3584 0% Number of IOs: 206 Number of bonded IOBs: 0 out of 141 0% Number of BRAMs: 16 out of 16 100% "ratemonotonic" <niladri1979@gmail.com> wrote in message = news:42df5ae8-8e9c-4475-983d-adc4c8c5b9f1@s8g2000prg.googlegroups.com...> On Dec 13, 12:23 pm, Brian Drummond <brian_drumm...@btconnect.com> > wrote: >> On Wed, 12 Dec 2007 07:49:18 -0800 (PST), ratemonotonic >> >> <niladri1...@gmail.com> wrote: >> >Hi All , >> >> >I am new to FPGA development and have learned VHDL using text books. >> >NOW! that doesn't teach practical aspects! >> >I am extremely confused with the following discovery - >> >> >Now the confusing part - I have designed an IP which consumes 15 >> >Block Rams , and when I include the IP in my microblaze system , the >> >bitstream gets generated! The synthesis report shows that my IP is >> >using up 15 Block Rams and that microblaze momories are using up 16 >> >Block Rams! That means that the system is using up 31 Block Rams! >> >> >How is that Possilbe? >> >> The final synthesis report probably shows about 190% of the BRAM >> resources are used. >> >> The synthesis output is valid - BUT - will not pass through the >> implementation tools until you either: redesign to use fewer =resources,>> or: target a bigger FPGA. >> >> If you don't want to re-design, low cost boards are available with =the>> Spartan-3 1500. Here's one... >> >> http://www.enterpoint.co.uk/moelbryn/raggedstone1.html >> >> - Brian >=20 > yes it is confusing because I am able to burn the logic and step > through the C code! > The system.mhh is as follows - >=20 >=20 >=20 > # > =#########################################################################= #####> # Created by Base System Builder Wizard for Xilinx EDK 9.2 Build > EDK_Jm.16 > # Tue Dec 11 11:23:35 2007 > # Target Board: Memec Spartan-3 3S400LC Development Board Rev 2 > # Family: spartan3 > # Device: XC3S400 > # Package: PQ208 > # Speed Grade: -4 > # Processor: microblaze_0 > # System clock frequency: 50.000000 MHz > # On Chip Memory : 16 KB > # > =#########################################################################= #####> PARAMETER VERSION =3D 2.1.0 >=20 >=20 > PORT fpga_0_RS232_RX_pin =3D fpga_0_RS232_RX, DIR =3D I > PORT fpga_0_RS232_TX_pin =3D fpga_0_RS232_TX, DIR =3D O > PORT fpga_0_DIP_Switches_4Bit_GPIO_in_pin =3D > fpga_0_DIP_Switches_4Bit_GPIO_in, DIR =3D I, VEC =3D [0:3] > PORT sys_clk_pin =3D dcm_clk_s, DIR =3D I, SIGIS =3D CLK, CLK_FREQ =3D > 50000000 > PORT sys_rst_pin =3D sys_rst_s, DIR =3D I, RST_POLARITY =3D 0, SIGIS ==3D RST>=20 >=20 > BEGIN microblaze > PARAMETER HW_VER =3D 7.00.a > PARAMETER INSTANCE =3D microblaze_0 > PARAMETER C_DEBUG_ENABLED =3D 1 > PARAMETER C_AREA_OPTIMIZED =3D 1 > PARAMETER C_FSL_LINKS =3D 1 > PARAMETER C_FAMILY =3D spartan3 > PARAMETER C_INSTANCE =3D microblaze_0 > BUS_INTERFACE DPLB =3D mb_plb > BUS_INTERFACE IPLB =3D mb_plb > BUS_INTERFACE DEBUG =3D microblaze_0_dbg > BUS_INTERFACE SFSL0 =3D modem_fsl_wrapper_0_to_microblaze_0_0 > BUS_INTERFACE DLMB =3D dlmb > BUS_INTERFACE ILMB =3D ilmb > BUS_INTERFACE MFSL0 =3D microblaze_0_to_modem_fsl_wrapper_0_0 > PORT RESET =3D mb_reset > PORT INTERRUPT =3D microblaze_0_INTERRUPT > END >=20 > BEGIN plb_v46 > PARAMETER INSTANCE =3D mb_plb > PARAMETER HW_VER =3D 1.00.a > PORT PLB_Clk =3D sys_clk_s > PORT SYS_Rst =3D sys_bus_reset > END >=20 > BEGIN lmb_v10 > PARAMETER INSTANCE =3D ilmb > PARAMETER HW_VER =3D 1.00.a > PORT LMB_Clk =3D sys_clk_s > PORT SYS_Rst =3D sys_bus_reset > END >=20 > BEGIN lmb_v10 > PARAMETER INSTANCE =3D dlmb > PARAMETER HW_VER =3D 1.00.a > PORT LMB_Clk =3D sys_clk_s > PORT SYS_Rst =3D sys_bus_reset > END >=20 > BEGIN lmb_bram_if_cntlr > PARAMETER INSTANCE =3D dlmb_cntlr > PARAMETER HW_VER =3D 2.10.a > PARAMETER C_BASEADDR =3D 0x00000000 > PARAMETER C_HIGHADDR =3D 0x00007FFF > BUS_INTERFACE SLMB =3D dlmb > BUS_INTERFACE BRAM_PORT =3D dlmb_cntlr_BRAM_PORT > END >=20 > BEGIN lmb_bram_if_cntlr > PARAMETER INSTANCE =3D ilmb_cntlr > PARAMETER HW_VER =3D 2.10.a > PARAMETER C_BASEADDR =3D 0x00000000 > PARAMETER C_HIGHADDR =3D 0x00007FFF > BUS_INTERFACE SLMB =3D ilmb > BUS_INTERFACE BRAM_PORT =3D ilmb_cntlr_BRAM_PORT > END >=20 > BEGIN bram_block > PARAMETER INSTANCE =3D lmb_bram > PARAMETER HW_VER =3D 1.00.a > BUS_INTERFACE PORTB =3D dlmb_cntlr_BRAM_PORT > BUS_INTERFACE PORTA =3D ilmb_cntlr_BRAM_PORT > END >=20 > BEGIN xps_uartlite > PARAMETER INSTANCE =3D RS232 > PARAMETER HW_VER =3D 1.00.a > PARAMETER C_BAUDRATE =3D 9600 > PARAMETER C_DATA_BITS =3D 8 > PARAMETER C_ODD_PARITY =3D 0 > PARAMETER C_USE_PARITY =3D 0 > PARAMETER C_SPLB_CLK_FREQ_HZ =3D 50000000 > PARAMETER C_BASEADDR =3D 0x83c12000 > PARAMETER C_HIGHADDR =3D 0x83c121ff > BUS_INTERFACE SPLB =3D mb_plb > PORT RX =3D fpga_0_RS232_RX > PORT TX =3D fpga_0_RS232_TX > END >=20 > BEGIN xps_gpio > PARAMETER INSTANCE =3D DIP_Switches_4Bit > PARAMETER HW_VER =3D 1.00.a > PARAMETER C_GPIO_WIDTH =3D 4 > PARAMETER C_IS_DUAL =3D 0 > PARAMETER C_ALL_INPUTS =3D 1 > PARAMETER C_IS_BIDIR =3D 0 > PARAMETER C_BASEADDR =3D 0x81400000 > PARAMETER C_HIGHADDR =3D 0x8140ffff > BUS_INTERFACE SPLB =3D mb_plb > PORT GPIO_in =3D fpga_0_DIP_Switches_4Bit_GPIO_in > END >=20 > BEGIN xps_timer > PARAMETER INSTANCE =3D timer_counter > PARAMETER HW_VER =3D 1.00.a > PARAMETER C_ONE_TIMER_ONLY =3D 1 > PARAMETER C_BASEADDR =3D 0x83c00000 > PARAMETER C_HIGHADDR =3D 0x83c0ffff > BUS_INTERFACE SPLB =3D mb_plb > PORT Interrupt =3D timer1 > PORT CaptureTrig0 =3D net_gnd > END >=20 > BEGIN clock_generator > PARAMETER INSTANCE =3D clock_generator_0 > PARAMETER HW_VER =3D 1.00.a > PARAMETER C_EXT_RESET_HIGH =3D 1 > PARAMETER C_CLKIN_FREQ =3D 50000000 > PARAMETER C_CLKOUT0_FREQ =3D 50000000 > PARAMETER C_CLKOUT0_PHASE =3D 0 > PARAMETER C_CLKOUT0_GROUP =3D NONE > PORT CLKOUT0 =3D sys_clk_s > PORT CLKIN =3D dcm_clk_s > PORT LOCKED =3D Dcm_all_locked > PORT RST =3D net_gnd > END >=20 > BEGIN mdm > PARAMETER INSTANCE =3D debug_module > PARAMETER HW_VER =3D 1.00.a > PARAMETER C_MB_DBG_PORTS =3D 1 > PARAMETER C_USE_UART =3D 1 > PARAMETER C_UART_WIDTH =3D 8 > PARAMETER C_BASEADDR =3D 0x84400000 > PARAMETER C_HIGHADDR =3D 0x8440ffff > BUS_INTERFACE SPLB =3D mb_plb > BUS_INTERFACE MBDEBUG_0 =3D microblaze_0_dbg > PORT Debug_SYS_Rst =3D Debug_SYS_Rst > END >=20 > BEGIN proc_sys_reset > PARAMETER INSTANCE =3D proc_sys_reset_0 > PARAMETER HW_VER =3D 2.00.a > PARAMETER C_EXT_RESET_HIGH =3D 0 > PORT Slowest_sync_clk =3D sys_clk_s > PORT Dcm_locked =3D Dcm_all_locked > PORT Ext_Reset_In =3D sys_rst_s > PORT MB_Reset =3D mb_reset > PORT Bus_Struct_Reset =3D sys_bus_reset > PORT MB_Debug_Sys_Rst =3D Debug_SYS_Rst > END >=20 > BEGIN fsl_v20 > PARAMETER INSTANCE =3D modem_fsl_wrapper_0_to_microblaze_0_0 > PARAMETER HW_VER =3D 2.11.a > PORT FSL_Clk =3D sys_clk_s > PORT SYS_Rst =3D net_gnd > END >=20 > BEGIN modem_fsl_wrapper > PARAMETER INSTANCE =3D modem_fsl_wrapper_0 > BUS_INTERFACE MFSL =3D modem_fsl_wrapper_0_to_microblaze_0_0 > BUS_INTERFACE SFSL =3D microblaze_0_to_modem_fsl_wrapper_0_0 > PORT FSL_Clk =3D sys_clk_s > END >=20 > BEGIN fsl_v20 > PARAMETER INSTANCE =3D microblaze_0_to_modem_fsl_wrapper_0_0 > PARAMETER HW_VER =3D 2.11.a > PORT FSL_Clk =3D sys_clk_s > PORT SYS_Rst =3D net_gnd > END >=20 > BEGIN xps_intc > PARAMETER INSTANCE =3D xps_intc_0 > PARAMETER HW_VER =3D 1.00.a > PARAMETER C_BASEADDR =3D 0x83c14000 > PARAMETER C_HIGHADDR =3D 0x83c141ff > BUS_INTERFACE SPLB =3D mb_plb > PORT Irq =3D microblaze_0_INTERRUPT > PORT Intr =3D timer1 > END >=20 > BEGIN util_vector_logic > PARAMETER INSTANCE =3D util_vector_logic_0 > PARAMETER HW_VER =3D 1.00.a > END >=20 > The guilty modules are - > 1)modem_fsl_wrapper whose device utilisation summary is - > Selected Device : 3s400pq208-4 >=20 > Number of Slices: 665 out of 3584 18% > Number of Slice Flip Flops: 841 out of 7168 11% > Number of 4 input LUTs: 995 out of 7168 13% > Number used as logic: 923 > Number used as Shift registers: 72 > Number of IOs: 140 > Number of bonded IOBs: 0 out of 141 0% > Number of BRAMs: 15 out of 16 93% > Number of MULT18X18s: 16 out of 16 100% > Number of GCLKs: 6 out of 8 75% > 2) Local BRAM - > device utilisatioin - > Device utilization summary: > --------------------------- >=20 > Selected Device : 3s400pq208-4 >=20 > Number of Slices: 0 out of 3584 0% > Number of IOs: 206 > Number of bonded IOBs: 0 out of 141 0% > Number of BRAMs: 16 out of 16 100% >=20 >=20 >=20 >=20 > Thanks for the guidance ! > BR > Rate------=_NextPart_000_0041_01C83E32.04930510 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML><HEAD> <META http-equiv=3DContent-Type content=3D"text/html; = charset=3Diso-8859-1"> <META content=3D"MSHTML 6.00.2900.3132" name=3DGENERATOR> <STYLE></STYLE> </HEAD> <BODY> <DIV><FONT face=3DArial size=3D2>Hi,</FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D1><FONT size=3D2>From your email</FONT> = <FONT size=3D2>I=20 found this.</FONT></FONT></DIV> <DIV><FONT face=3DArial size=3D2>It looks everything has been trimmed = away since you=20 are using 0% slices and 0 pads.</FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2>If you look at the system_map.mrp file, = there is a=20 section on what has been trimmed away.</FONT></DIV> <DIV><FONT face=3DArial size=3D2>That could give you a hint what is = causing this.=20 You might also add the option "-detail" to the map tool.</FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2>G=F6ran</FONT></DIV> <DIV><FONT face=3DArial size=3D2><EM><FONT = size=3D1></FONT></EM></FONT> </DIV> <DIV><FONT face=3DArial size=3D2><EM><FONT size=3D1>Device utilization=20 summary:<BR>---------------------------<BR><BR>Selected Device :=20 3s400pq208-4<BR><BR> Number of=20 Slices: = =20 0 out of 3584 = 0%<BR> Number of=20 IOs: &nb= sp; =20 206<BR> Number of bonded=20 IOBs: &n= bsp; =20 0 out of 141 = 0%<BR> Number=20 of=20 BRAMs: &= nbsp; =20 16 out of 16 =20 100%</FONT></EM><BR></DIV></FONT> <DIV><FONT face=3DArial size=3D2>"ratemonotonic" <</FONT><A=20 href=3D"mailto:niladri1979@gmail.com"><FONT face=3DArial=20 size=3D2>niladri1979@gmail.com</FONT></A><FONT face=3DArial = size=3D2>> wrote in=20 message </FONT><A=20 href=3D"news:42df5ae8-8e9c-4475-983d-adc4c8c5b9f1@s8g2000prg.googlegroups= .com"><FONT=20 face=3DArial=20 size=3D2>news:42df5ae8-8e9c-4475-983d-adc4c8c5b9f1@s8g2000prg.googlegroup= s.com</FONT></A><FONT=20 face=3DArial size=3D2>...</FONT></DIV><FONT face=3DArial size=3D2>> = On Dec 13, 12:23=20 pm, Brian Drummond <</FONT><A=20 href=3D"mailto:brian_drumm...@btconnect.com"><FONT face=3DArial=20 size=3D2>brian_drumm...@btconnect.com</FONT></A><FONT face=3DArial=20 size=3D2>><BR>> wrote:<BR>>> On Wed, 12 Dec 2007 07:49:18 = -0800 (PST),=20 ratemonotonic<BR>>><BR>>> <</FONT><A=20 href=3D"mailto:niladri1...@gmail.com"><FONT face=3DArial=20 size=3D2>niladri1...@gmail.com</FONT></A><FONT face=3DArial = size=3D2>>=20 wrote:<BR>>> >Hi All ,<BR>>><BR>>> >I am new to = FPGA=20 development and have learned VHDL using text books.<BR>>> >NOW! = that=20 doesn't teach practical aspects!<BR>>> >I am extremely confused = with=20 the following discovery -<BR>>><BR>>> >Now the confusing = part=20 - I have designed an IP which consumes 15<BR>>> >Block = Rams , and=20 when I include the IP in my microblaze system , the<BR>>> = >bitstream=20 gets generated! The synthesis report shows that my IP is<BR>>> = >using=20 up 15 Block Rams and that microblaze momories are using up = 16<BR>>>=20 >Block Rams! That means that the system is using up 31 Block=20 Rams!<BR>>><BR>>> >How is that = Possilbe?<BR>>><BR>>>=20 The final synthesis report probably shows about 190% of the = BRAM<BR>>>=20 resources are used.<BR>>><BR>>> The synthesis output is = valid - BUT=20 - will not pass through the<BR>>> implementation tools until you = either:=20 redesign to use fewer resources,<BR>>> or: target a bigger=20 FPGA.<BR>>><BR>>> If you don't want to re-design, low cost = boards=20 are available with the<BR>>> Spartan-3 1500. Here's=20 one...<BR>>><BR>>> </FONT><A=20 href=3D"http://www.enterpoint.co.uk/moelbryn/raggedstone1.html"><FONT = face=3DArial=20 size=3D2>http://www.enterpoint.co.uk/moelbryn/raggedstone1.html</FONT></A=><BR><FONT=20face=3DArial size=3D2>>><BR>>> - Brian<BR>> <BR>> yes = it is=20 confusing because I am able to burn the logic and step<BR>> through = the C=20 code!<BR>> The system.mhh is as follows -<BR>> <BR>> <BR>> = <BR>>=20 #<BR>>=20 #########################################################################= #####<BR>>=20 # Created by Base System Builder Wizard for Xilinx EDK 9.2 Build<BR>> = EDK_Jm.16<BR>> # Tue Dec 11 11:23:35 2007<BR>> # Target = Board: Memec=20 Spartan-3 3S400LC Development Board Rev 2<BR>> # Family: = spartan3<BR>> #=20 Device: XC3S400<BR>> # Package: PQ208<BR>> # Speed Grade: = -4<BR>> #=20 Processor: microblaze_0<BR>> # System clock frequency: 50.000000 = MHz<BR>>=20 # On Chip Memory : 16 KB<BR>> #<BR>>=20 #########################################################################= #####<BR>> PARAMETER=20 VERSION =3D 2.1.0<BR>> <BR>> <BR>> PORT = fpga_0_RS232_RX_pin =3D=20 fpga_0_RS232_RX, DIR =3D I<BR>> PORT fpga_0_RS232_TX_pin =3D=20 fpga_0_RS232_TX, DIR =3D O<BR>> PORT = fpga_0_DIP_Switches_4Bit_GPIO_in_pin=20 =3D<BR>> fpga_0_DIP_Switches_4Bit_GPIO_in, DIR =3D I, VEC =3D=20 [0:3]<BR>> PORT sys_clk_pin =3D dcm_clk_s, DIR =3D I, SIGIS =3D = CLK, CLK_FREQ=20 =3D<BR>> 50000000<BR>> PORT sys_rst_pin =3D sys_rst_s, DIR = =3D I,=20 RST_POLARITY =3D 0, SIGIS =3D RST<BR>> <BR>> <BR>> BEGIN=20 microblaze<BR>> PARAMETER HW_VER =3D = 7.00.a<BR>> PARAMETER=20 INSTANCE =3D microblaze_0<BR>> PARAMETER C_DEBUG_ENABLED =3D=20 1<BR>> PARAMETER C_AREA_OPTIMIZED =3D 1<BR>> PARAMETER = C_FSL_LINKS=20 =3D 1<BR>> PARAMETER C_FAMILY =3D = spartan3<BR>> PARAMETER C_INSTANCE=20 =3D microblaze_0<BR>> BUS_INTERFACE DPLB =3D=20 mb_plb<BR>> BUS_INTERFACE IPLB =3D = mb_plb<BR>> BUS_INTERFACE DEBUG=20 =3D microblaze_0_dbg<BR>> BUS_INTERFACE SFSL0 =3D=20 modem_fsl_wrapper_0_to_microblaze_0_0<BR>> BUS_INTERFACE DLMB = =3D=20 dlmb<BR>> BUS_INTERFACE ILMB =3D ilmb<BR>> BUS_INTERFACE = MFSL0 =3D=20 microblaze_0_to_modem_fsl_wrapper_0_0<BR>> PORT RESET =3D=20 mb_reset<BR>> PORT INTERRUPT =3D microblaze_0_INTERRUPT<BR>>=20 END<BR>> <BR>> BEGIN plb_v46<BR>> PARAMETER INSTANCE =3D=20 mb_plb<BR>> PARAMETER HW_VER =3D 1.00.a<BR>> PORT = PLB_Clk =3D=20 sys_clk_s<BR>> PORT SYS_Rst =3D sys_bus_reset<BR>> = END<BR>> <BR>>=20 BEGIN lmb_v10<BR>> PARAMETER INSTANCE =3D = ilmb<BR>> PARAMETER=20 HW_VER =3D 1.00.a<BR>> PORT LMB_Clk =3D = sys_clk_s<BR>> PORT SYS_Rst=20 =3D sys_bus_reset<BR>> END<BR>> <BR>> BEGIN=20 lmb_v10<BR>> PARAMETER INSTANCE =3D dlmb<BR>> PARAMETER = HW_VER =3D=20 1.00.a<BR>> PORT LMB_Clk =3D sys_clk_s<BR>> PORT SYS_Rst = =3D=20 sys_bus_reset<BR>> END<BR>> <BR>> BEGIN=20 lmb_bram_if_cntlr<BR>> PARAMETER INSTANCE =3D=20 dlmb_cntlr<BR>> PARAMETER HW_VER =3D = 2.10.a<BR>> PARAMETER=20 C_BASEADDR =3D 0x00000000<BR>> PARAMETER C_HIGHADDR =3D=20 0x00007FFF<BR>> BUS_INTERFACE SLMB =3D = dlmb<BR>> BUS_INTERFACE=20 BRAM_PORT =3D dlmb_cntlr_BRAM_PORT<BR>> END<BR>> <BR>> BEGIN=20 lmb_bram_if_cntlr<BR>> PARAMETER INSTANCE =3D=20 ilmb_cntlr<BR>> PARAMETER HW_VER =3D = 2.10.a<BR>> PARAMETER=20 C_BASEADDR =3D 0x00000000<BR>> PARAMETER C_HIGHADDR =3D=20 0x00007FFF<BR>> BUS_INTERFACE SLMB =3D = ilmb<BR>> BUS_INTERFACE=20 BRAM_PORT =3D ilmb_cntlr_BRAM_PORT<BR>> END<BR>> <BR>> BEGIN=20 bram_block<BR>> PARAMETER INSTANCE =3D = lmb_bram<BR>> PARAMETER=20 HW_VER =3D 1.00.a<BR>> BUS_INTERFACE PORTB =3D=20 dlmb_cntlr_BRAM_PORT<BR>> BUS_INTERFACE PORTA =3D=20 ilmb_cntlr_BRAM_PORT<BR>> END<BR>> <BR>> BEGIN=20 xps_uartlite<BR>> PARAMETER INSTANCE =3D = RS232<BR>> PARAMETER=20 HW_VER =3D 1.00.a<BR>> PARAMETER C_BAUDRATE =3D = 9600<BR>> PARAMETER=20 C_DATA_BITS =3D 8<BR>> PARAMETER C_ODD_PARITY =3D = 0<BR>> PARAMETER=20 C_USE_PARITY =3D 0<BR>> PARAMETER C_SPLB_CLK_FREQ_HZ =3D=20 50000000<BR>> PARAMETER C_BASEADDR =3D = 0x83c12000<BR>> PARAMETER=20 C_HIGHADDR =3D 0x83c121ff<BR>> BUS_INTERFACE SPLB =3D=20 mb_plb<BR>> PORT RX =3D fpga_0_RS232_RX<BR>> PORT TX =3D = fpga_0_RS232_TX<BR>> END<BR>> <BR>> BEGIN=20 xps_gpio<BR>> PARAMETER INSTANCE =3D=20 DIP_Switches_4Bit<BR>> PARAMETER HW_VER =3D = 1.00.a<BR>> PARAMETER=20 C_GPIO_WIDTH =3D 4<BR>> PARAMETER C_IS_DUAL =3D = 0<BR>> PARAMETER=20 C_ALL_INPUTS =3D 1<BR>> PARAMETER C_IS_BIDIR =3D = 0<BR>> PARAMETER=20 C_BASEADDR =3D 0x81400000<BR>> PARAMETER C_HIGHADDR =3D=20 0x8140ffff<BR>> BUS_INTERFACE SPLB =3D mb_plb<BR>> PORT = GPIO_in =3D=20 fpga_0_DIP_Switches_4Bit_GPIO_in<BR>> END<BR>> <BR>> BEGIN=20 xps_timer<BR>> PARAMETER INSTANCE =3D = timer_counter<BR>> PARAMETER=20 HW_VER =3D 1.00.a<BR>> PARAMETER C_ONE_TIMER_ONLY =3D=20 1<BR>> PARAMETER C_BASEADDR =3D = 0x83c00000<BR>> PARAMETER=20 C_HIGHADDR =3D 0x83c0ffff<BR>> BUS_INTERFACE SPLB =3D=20 mb_plb<BR>> PORT Interrupt =3D timer1<BR>> PORT = CaptureTrig0 =3D=20 net_gnd<BR>> END<BR>> <BR>> BEGIN=20 clock_generator<BR>> PARAMETER INSTANCE =3D=20 clock_generator_0<BR>> PARAMETER HW_VER =3D = 1.00.a<BR>> PARAMETER=20 C_EXT_RESET_HIGH =3D 1<BR>> PARAMETER C_CLKIN_FREQ =3D=20 50000000<BR>> PARAMETER C_CLKOUT0_FREQ =3D = 50000000<BR>> PARAMETER=20 C_CLKOUT0_PHASE =3D 0<BR>> PARAMETER C_CLKOUT0_GROUP =3D=20 NONE<BR>> PORT CLKOUT0 =3D sys_clk_s<BR>> PORT CLKIN =3D = dcm_clk_s<BR>> PORT LOCKED =3D Dcm_all_locked<BR>> PORT = RST =3D=20 net_gnd<BR>> END<BR>> <BR>> BEGIN mdm<BR>> PARAMETER = INSTANCE =3D=20 debug_module<BR>> PARAMETER HW_VER =3D = 1.00.a<BR>> PARAMETER=20 C_MB_DBG_PORTS =3D 1<BR>> PARAMETER C_USE_UART =3D = 1<BR>> PARAMETER=20 C_UART_WIDTH =3D 8<BR>> PARAMETER C_BASEADDR =3D=20 0x84400000<BR>> PARAMETER C_HIGHADDR =3D=20 0x8440ffff<BR>> BUS_INTERFACE SPLB =3D = mb_plb<BR>> BUS_INTERFACE=20 MBDEBUG_0 =3D microblaze_0_dbg<BR>> PORT Debug_SYS_Rst =3D=20 Debug_SYS_Rst<BR>> END<BR>> <BR>> BEGIN=20 proc_sys_reset<BR>> PARAMETER INSTANCE =3D=20 proc_sys_reset_0<BR>> PARAMETER HW_VER =3D = 2.00.a<BR>> PARAMETER=20 C_EXT_RESET_HIGH =3D 0<BR>> PORT Slowest_sync_clk =3D=20 sys_clk_s<BR>> PORT Dcm_locked =3D = Dcm_all_locked<BR>> PORT=20 Ext_Reset_In =3D sys_rst_s<BR>> PORT MB_Reset =3D = mb_reset<BR>> PORT=20 Bus_Struct_Reset =3D sys_bus_reset<BR>> PORT MB_Debug_Sys_Rst = =3D=20 Debug_SYS_Rst<BR>> END<BR>> <BR>> BEGIN = fsl_v20<BR>> PARAMETER=20 INSTANCE =3D = modem_fsl_wrapper_0_to_microblaze_0_0<BR>> PARAMETER HW_VER =3D=20 2.11.a<BR>> PORT FSL_Clk =3D sys_clk_s<BR>> PORT SYS_Rst = =3D=20 net_gnd<BR>> END<BR>> <BR>> BEGIN=20 modem_fsl_wrapper<BR>> PARAMETER INSTANCE =3D=20 modem_fsl_wrapper_0<BR>> BUS_INTERFACE MFSL =3D=20 modem_fsl_wrapper_0_to_microblaze_0_0<BR>> BUS_INTERFACE SFSL = =3D=20 microblaze_0_to_modem_fsl_wrapper_0_0<BR>> PORT FSL_Clk =3D=20 sys_clk_s<BR>> END<BR>> <BR>> BEGIN = fsl_v20<BR>> PARAMETER=20 INSTANCE =3D = microblaze_0_to_modem_fsl_wrapper_0_0<BR>> PARAMETER HW_VER =3D=20 2.11.a<BR>> PORT FSL_Clk =3D sys_clk_s<BR>> PORT SYS_Rst = =3D=20 net_gnd<BR>> END<BR>> <BR>> BEGIN = xps_intc<BR>> PARAMETER=20 INSTANCE =3D xps_intc_0<BR>> PARAMETER HW_VER =3D=20 1.00.a<BR>> PARAMETER C_BASEADDR =3D = 0x83c14000<BR>> PARAMETER=20 C_HIGHADDR =3D 0x83c141ff<BR>> BUS_INTERFACE SPLB =3D=20 mb_plb<BR>> PORT Irq =3D = microblaze_0_INTERRUPT<BR>> PORT Intr =3D=20 timer1<BR>> END<BR>> <BR>> BEGIN=20 util_vector_logic<BR>> PARAMETER INSTANCE =3D=20 util_vector_logic_0<BR>> PARAMETER HW_VER =3D 1.00.a<BR>> = END<BR>>=20 <BR>> The guilty modules are -<BR>> 1)modem_fsl_wrapper = whose device=20 utilisation summary is -<BR>> Selected Device : 3s400pq208-4<BR>>=20 <BR>> Number of=20 Slices: = =20 665 out of 3584 = 18%<BR>> Number of=20 Slice Flip = Flops: =20 841 out of 7168 = 11%<BR>> Number of 4=20 input=20 LUTs: &n= bsp; =20 995 out of 7168 =20 13%<BR>> Number used as=20 logic: &= nbsp; =20 923<BR>> Number used as Shift=20 registers: 72<BR>> Number of=20 IOs: &nb= sp; =20 140<BR>> Number of bonded=20 IOBs: &n= bsp; =20 0 out of 141 =20 0%<BR>> Number of=20 BRAMs: &= nbsp; =20 15 out of 16 =20 93%<BR>> Number of=20 MULT18X18s: &n= bsp; =20 16 out of 16 = 100%<BR>> Number=20 of=20 GCLKs: &= nbsp; =20 6 out of 8 = 75%<BR>> 2)=20 Local BRAM -<BR>> device utilisatioin -<BR>> Device utilization=20 summary:<BR>> ---------------------------<BR>> <BR>> Selected = Device :=20 3s400pq208-4<BR>> <BR>> Number of=20 Slices: = =20 0 out of 3584 = 0%<BR>> Number=20 of=20 IOs: &nb= sp; =20 206<BR>> Number of bonded=20 IOBs: &n= bsp; =20 0 out of 141 =20 0%<BR>> Number of=20 BRAMs: &= nbsp; =20 16 out of 16 100%<BR>> = <BR>>=20 <BR>> <BR>> <BR>> Thanks for the guidance !<BR>> BR<BR>>=20 Rate</FONT></BODY></HTML> ------=_NextPart_000_0041_01C83E32.04930510--
Reply by ●December 14, 20072007-12-14
On Thu, 13 Dec 2007 08:19:26 -0800 (PST), ratemonotonic <niladri1979@gmail.com> wrote:>On Dec 13, 12:23 pm, Brian Drummond <brian_drumm...@btconnect.com> >wrote: >> On Wed, 12 Dec 2007 07:49:18 -0800 (PST), ratemonotonic >>>> The synthesis output is valid - BUT - will not pass through the >> implementation tools until you either: redesign to use fewer resources, >> or: target a bigger FPGA.>spartan 3 400 has 56Kbit distributed RAM is it possible that the >synthesizer is using then as block RAMs as well?Not if your design specifically calls for BRAMS, so not likely. In any case it would appear in the synth report and map.mrp as "LUTs used as memory" or equivalent wording. I am confused by the separate synthesis reports yu posted for modem_wrapper and local_bram ... are you synthesising the two separately? If so, how are you combining them into one project? Is this built entirely under EDK or are you combining an EDK design with an XST design? It is possible that something is going wrong with that step; apparently leaving you with a working Microblaze so presumably no modem... you have to get through this step to correctly fail, THEN worry about economising memory. - Brian
