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multidimensional arrays in VHDL?

Started by Anuja ●December 17, 2007
I am trying to covert the following Verilog code to VHDL. I am having
issues with converting the arrays to VHDL. Could you please comment on
how this should be done
module FIFO16x8(DataOut, DataIn, FF, AF, HF, AE, EF, Push, Pop, Dump,
Clk);
	parameter WIDTH = 8;
	parameter DEPTH = 16;
	parameter LOG2DEPTH = 4;

	input [(WIDTH-1):0] DataIn;
	output [(WIDTH-1):0] DataOut;
	output FF, AF, HF, AE, EF;
	input Push, Pop, Dump, Clk;

	wire WE, RE;

	reg [(LOG2DEPTH-1):0] Contents, ReadPointer, WritePointer;
	reg [(WIDTH-1):0] queue[(DEPTH-1):0];

	assign FF = (Contents == (DEPTH-1))? 1 : 0;
	assign AF = (Contents > (DEPTH-3))? 1 : 0;
	assign HF = (Contents > (DEPTH/2))? 1 : 0;
	assign AE = (Contents < 3)? 1 : 0;
	assign EF = (Contents == 0)? 1 : 0;

	assign WE = Push && ~FF;
	assign RE = Pop && ~EF;

	assign DataOut = queue[ReadPointer];

	always @ (posedge Clk)
	begin
		if (Dump == 1)
			Contents <= 0;
		else
			if ((WE == 1) && (RE == 0))
				Contents <= Contents + 1;
			else
				if ((WE == 0) && (RE == 1))
					Contents <= Contents - 1;
				else
					Contents <= Contents;
	end

	always @ (posedge Clk)
	begin
		if (Dump == 1)
			begin
				ReadPointer <= 0;
				WritePointer <= 0;
			end
		else
			begin
				if (RE == 1)
					begin
						ReadPointer <= ReadPointer + 1;
					end
				if (WE == 1)
					begin
						queue[WritePointer] <= DataIn;
						WritePointer <= WritePointer + 1;
					end
			end
	end

endmodule


I have declared an array in VHDL as follows
TYPE queue IS ARRAY (7 DOWNTO 0, 15 DOWNTO 0)
	                              OF std_logic_vector(7 downto 0);

I am not sure about how to convert the Verilog statements belwo to
VHDL. Verilog code is referenced above.
assign DataOut = queue[ReadPointer];
and
queue[WritePointer] <= DataIn;

thanks
Anuja
Reply by sudhi ●December 17, 20072007-12-17
On Dec 17, 2:04 pm, Anuja <thakkar.an...@gmail.com> wrote:

> I am trying to covert the following Verilog code to VHDL. I am having
> issues with converting the arrays to VHDL. Could you please comment on
> how this should be done
> module FIFO16x8(DataOut, DataIn, FF, AF, HF, AE, EF, Push, Pop, Dump,
> Clk);
>         parameter WIDTH = 8;
>         parameter DEPTH = 16;
>         parameter LOG2DEPTH = 4;
>
>         input [(WIDTH-1):0] DataIn;
>         output [(WIDTH-1):0] DataOut;
>         output FF, AF, HF, AE, EF;
>         input Push, Pop, Dump, Clk;
>
>         wire WE, RE;
>
>         reg [(LOG2DEPTH-1):0] Contents, ReadPointer, WritePointer;
>         reg [(WIDTH-1):0] queue[(DEPTH-1):0];
>
>         assign FF = (Contents == (DEPTH-1))? 1 : 0;
>         assign AF = (Contents > (DEPTH-3))? 1 : 0;
>         assign HF = (Contents > (DEPTH/2))? 1 : 0;
>         assign AE = (Contents < 3)? 1 : 0;
>         assign EF = (Contents == 0)? 1 : 0;
>
>         assign WE = Push && ~FF;
>         assign RE = Pop && ~EF;
>
>         assign DataOut = queue[ReadPointer];
>
>         always @ (posedge Clk)
>         begin
>                 if (Dump == 1)
>                         Contents <= 0;
>                 else
>                         if ((WE == 1) && (RE == 0))
>                                 Contents <= Contents + 1;
>                         else
>                                 if ((WE == 0) && (RE == 1))
>                                         Contents <= Contents - 1;
>                                 else
>                                         Contents <= Contents;
>         end
>
>         always @ (posedge Clk)
>         begin
>                 if (Dump == 1)
>                         begin
>                                 ReadPointer <= 0;
>                                 WritePointer <= 0;
>                         end
>                 else
>                         begin
>                                 if (RE == 1)
>                                         begin
>                                                 ReadPointer <= ReadPointer + 1;
>                                         end
>                                 if (WE == 1)
>                                         begin
>                                                 queue[WritePointer] <= DataIn;
>                                                 WritePointer <= WritePointer + 1;
>                                         end
>                         end
>         end
>
> endmodule
>
> I have declared an array in VHDL as follows
> TYPE queue IS ARRAY (7 DOWNTO 0, 15 DOWNTO 0)
>                                       OF std_logic_vector(7 downto 0);
>
> I am not sure about how to convert the Verilog statements belwo to
> VHDL. Verilog code is referenced above.
> assign DataOut = queue[ReadPointer];
> and
> queue[WritePointer] <= DataIn;
>
> thanks
> Anuja


Use,

TYPE queue IS ARRAY(15 DOWNTO 0) OF std_logic_vector(7 DOWNTO 0);

Since your read and write pointers are std_logic_vectors, they cannot
be used for indexing into and array. Convert them to integers using
the functions in numeric_std package like so

DataOut <= queue(to_integer(ReadPointer));

and

queue(to_integer(WritePointer)) <= DataIn;

Hope this helps,
Sudheendra Kadri
Reply by Anuja ●December 17, 20072007-12-17
On Dec 17, 4:30 pm, sudhi <sudhi.ka...@gmail.com> wrote:

> On Dec 17, 2:04 pm, Anuja <thakkar.an...@gmail.com> wrote:
>
>
>
>
>
> > I am trying to covert the following Verilog code to VHDL. I am having
> > issues with converting the arrays to VHDL. Could you please comment on
> > how this should be done
> > module FIFO16x8(DataOut, DataIn, FF, AF, HF, AE, EF, Push, Pop, Dump,
> > Clk);
> >         parameter WIDTH = 8;
> >         parameter DEPTH = 16;
> >         parameter LOG2DEPTH = 4;
>
> >         input [(WIDTH-1):0] DataIn;
> >         output [(WIDTH-1):0] DataOut;
> >         output FF, AF, HF, AE, EF;
> >         input Push, Pop, Dump, Clk;
>
> >         wire WE, RE;
>
> >         reg [(LOG2DEPTH-1):0] Contents, ReadPointer, WritePointer;
> >         reg [(WIDTH-1):0] queue[(DEPTH-1):0];
>
> >         assign FF = (Contents == (DEPTH-1))? 1 : 0;
> >         assign AF = (Contents > (DEPTH-3))? 1 : 0;
> >         assign HF = (Contents > (DEPTH/2))? 1 : 0;
> >         assign AE = (Contents < 3)? 1 : 0;
> >         assign EF = (Contents == 0)? 1 : 0;
>
> >         assign WE = Push && ~FF;
> >         assign RE = Pop && ~EF;
>
> >         assign DataOut = queue[ReadPointer];
>
> >         always @ (posedge Clk)
> >         begin
> >                 if (Dump == 1)
> >                         Contents <= 0;
> >                 else
> >                         if ((WE == 1) && (RE == 0))
> >                                 Contents <= Contents + 1;
> >                         else
> >                                 if ((WE == 0) && (RE == 1))
> >                                         Contents <= Contents - 1;
> >                                 else
> >                                         Contents <= Contents;
> >         end
>
> >         always @ (posedge Clk)
> >         begin
> >                 if (Dump == 1)
> >                         begin
> >                                 ReadPointer <= 0;
> >                                 WritePointer <= 0;
> >                         end
> >                 else
> >                         begin
> >                                 if (RE == 1)
> >                                         begin
> >                                                 ReadPointer <= ReadPointer + 1;
> >                                         end
> >                                 if (WE == 1)
> >                                         begin
> >                                                 queue[WritePointer] <= DataIn;
> >                                                 WritePointer <= WritePointer + 1;
> >                                         end
> >                         end
> >         end
>
> > endmodule
>
> > I have declared an array in VHDL as follows
> > TYPE queue IS ARRAY (7 DOWNTO 0, 15 DOWNTO 0)
> >                                       OF std_logic_vector(7 downto 0);
>
> > I am not sure about how to convert the Verilog statements belwo to
> > VHDL. Verilog code is referenced above.
> > assign DataOut = queue[ReadPointer];
> > and
> > queue[WritePointer] <= DataIn;
>
> > thanks
> > Anuja
>
> Use,
>
> TYPE queue IS ARRAY(15 DOWNTO 0) OF std_logic_vector(7 DOWNTO 0);
>
> Since your read and write pointers are std_logic_vectors, they cannot
> be used for indexing into and array. Convert them to integers using
> the functions in numeric_std package like so
>
> DataOut <= queue(to_integer(ReadPointer));
>
> and
>
> queue(to_integer(WritePointer)) <= DataIn;
>
> Hope this helps,
> Sudheendra Kadri- Hide quoted text -
>
> - Show quoted text -


Shouldnt the array be multidimensional? Isnt the array you defined one
dimensional?
Reply by Anuja ●December 17, 20072007-12-17
On Dec 17, 4:39 pm, Anuja <thakkar.an...@gmail.com> wrote:

> On Dec 17, 4:30 pm, sudhi <sudhi.ka...@gmail.com> wrote:
>
>
>
>
>
> > On Dec 17, 2:04 pm, Anuja <thakkar.an...@gmail.com> wrote:
>
> > > I am trying to covert the following Verilog code to VHDL. I am having
> > > issues with converting the arrays to VHDL. Could you please comment on
> > > how this should be done
> > > module FIFO16x8(DataOut, DataIn, FF, AF, HF, AE, EF, Push, Pop, Dump,
> > > Clk);
> > >         parameter WIDTH = 8;
> > >         parameter DEPTH = 16;
> > >         parameter LOG2DEPTH = 4;
>
> > >         input [(WIDTH-1):0] DataIn;
> > >         output [(WIDTH-1):0] DataOut;
> > >         output FF, AF, HF, AE, EF;
> > >         input Push, Pop, Dump, Clk;
>
> > >         wire WE, RE;
>
> > >         reg [(LOG2DEPTH-1):0] Contents, ReadPointer, WritePointer;
> > >         reg [(WIDTH-1):0] queue[(DEPTH-1):0];
>
> > >         assign FF = (Contents == (DEPTH-1))? 1 : 0;
> > >         assign AF = (Contents > (DEPTH-3))? 1 : 0;
> > >         assign HF = (Contents > (DEPTH/2))? 1 : 0;
> > >         assign AE = (Contents < 3)? 1 : 0;
> > >         assign EF = (Contents == 0)? 1 : 0;
>
> > >         assign WE = Push && ~FF;
> > >         assign RE = Pop && ~EF;
>
> > >         assign DataOut = queue[ReadPointer];
>
> > >         always @ (posedge Clk)
> > >         begin
> > >                 if (Dump == 1)
> > >                         Contents <= 0;
> > >                 else
> > >                         if ((WE == 1) && (RE == 0))
> > >                                 Contents <= Contents + 1;
> > >                         else
> > >                                 if ((WE == 0) && (RE == 1))
> > >                                         Contents <= Contents - 1;
> > >                                 else
> > >                                         Contents <= Contents;
> > >         end
>
> > >         always @ (posedge Clk)
> > >         begin
> > >                 if (Dump == 1)
> > >                         begin
> > >                                 ReadPointer <= 0;
> > >                                 WritePointer <= 0;
> > >                         end
> > >                 else
> > >                         begin
> > >                                 if (RE == 1)
> > >                                         begin
> > >                                                 ReadPointer <= ReadPointer + 1;
> > >                                         end
> > >                                 if (WE == 1)
> > >                                         begin
> > >                                                 queue[WritePointer] <= DataIn;
> > >                                                 WritePointer <= WritePointer + 1;
> > >                                         end
> > >                         end
> > >         end
>
> > > endmodule
>
> > > I have declared an array in VHDL as follows
> > > TYPE queue IS ARRAY (7 DOWNTO 0, 15 DOWNTO 0)
> > >                                       OF std_logic_vector(7 downto 0);
>
> > > I am not sure about how to convert the Verilog statements belwo to
> > > VHDL. Verilog code is referenced above.
> > > assign DataOut = queue[ReadPointer];
> > > and
> > > queue[WritePointer] <= DataIn;
>
> > > thanks
> > > Anuja
>
> > Use,
>
> > TYPE queue IS ARRAY(15 DOWNTO 0) OF std_logic_vector(7 DOWNTO 0);
>
> > Since your read and write pointers are std_logic_vectors, they cannot
> > be used for indexing into and array. Convert them to integers using
> > the functions in numeric_std package like so
>
> > DataOut <= queue(to_integer(ReadPointer));
>
> > and
>
> > queue(to_integer(WritePointer)) <= DataIn;
>
> > Hope this helps,
> > Sudheendra Kadri- Hide quoted text -
>
> > - Show quoted text -
>
> Shouldnt the array be multidimensional? Isnt the array you defined one
> dimensional?- Hide quoted text -
>
> - Show quoted text -


I am getting the following error message
No feasible entries for subprogram "to_integer".

I HAVE INCLUDED NUMERIC_STD package as follows

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.numeric_std.ALL;

It also comlained about target of signal assignment is not a signal.
So, I defined q_queue of type queue(array) and that was solved.
Reply by sudhi ●December 17, 20072007-12-17
On Dec 17, 2:53 pm, Anuja <thakkar.an...@gmail.com> wrote:

> On Dec 17, 4:39 pm, Anuja <thakkar.an...@gmail.com> wrote:
>
>
>
> > On Dec 17, 4:30 pm, sudhi <sudhi.ka...@gmail.com> wrote:
>
> > > On Dec 17, 2:04 pm, Anuja <thakkar.an...@gmail.com> wrote:
>
> > > > I am trying to covert the following Verilog code to VHDL. I am having
> > > > issues with converting the arrays to VHDL. Could you please comment on
> > > > how this should be done
> > > > module FIFO16x8(DataOut, DataIn, FF, AF, HF, AE, EF, Push, Pop, Dump,
> > > > Clk);
> > > >         parameter WIDTH = 8;
> > > >         parameter DEPTH = 16;
> > > >         parameter LOG2DEPTH = 4;
>
> > > >         input [(WIDTH-1):0] DataIn;
> > > >         output [(WIDTH-1):0] DataOut;
> > > >         output FF, AF, HF, AE, EF;
> > > >         input Push, Pop, Dump, Clk;
>
> > > >         wire WE, RE;
>
> > > >         reg [(LOG2DEPTH-1):0] Contents, ReadPointer, WritePointer;
> > > >         reg [(WIDTH-1):0] queue[(DEPTH-1):0];
>
> > > >         assign FF = (Contents == (DEPTH-1))? 1 : 0;
> > > >         assign AF = (Contents > (DEPTH-3))? 1 : 0;
> > > >         assign HF = (Contents > (DEPTH/2))? 1 : 0;
> > > >         assign AE = (Contents < 3)? 1 : 0;
> > > >         assign EF = (Contents == 0)? 1 : 0;
>
> > > >         assign WE = Push && ~FF;
> > > >         assign RE = Pop && ~EF;
>
> > > >         assign DataOut = queue[ReadPointer];
>
> > > >         always @ (posedge Clk)
> > > >         begin
> > > >                 if (Dump == 1)
> > > >                         Contents <= 0;
> > > >                 else
> > > >                         if ((WE == 1) && (RE == 0))
> > > >                                 Contents <= Contents + 1;
> > > >                         else
> > > >                                 if ((WE == 0) && (RE == 1))
> > > >                                         Contents <= Contents - 1;
> > > >                                 else
> > > >                                         Contents <= Contents;
> > > >         end
>
> > > >         always @ (posedge Clk)
> > > >         begin
> > > >                 if (Dump == 1)
> > > >                         begin
> > > >                                 ReadPointer <= 0;
> > > >                                 WritePointer <= 0;
> > > >                         end
> > > >                 else
> > > >                         begin
> > > >                                 if (RE == 1)
> > > >                                         begin
> > > >                                                 ReadPointer <= ReadPointer + 1;
> > > >                                         end
> > > >                                 if (WE == 1)
> > > >                                         begin
> > > >                                                 queue[WritePointer] <= DataIn;
> > > >                                                 WritePointer <= WritePointer + 1;
> > > >                                         end
> > > >                         end
> > > >         end
>
> > > > endmodule
>
> > > > I have declared an array in VHDL as follows
> > > > TYPE queue IS ARRAY (7 DOWNTO 0, 15 DOWNTO 0)
> > > >                                       OF std_logic_vector(7 downto 0);
>
> > > > I am not sure about how to convert the Verilog statements belwo to
> > > > VHDL. Verilog code is referenced above.
> > > > assign DataOut = queue[ReadPointer];
> > > > and
> > > > queue[WritePointer] <= DataIn;
>
> > > > thanks
> > > > Anuja
>
> > > Use,
>
> > > TYPE queue IS ARRAY(15 DOWNTO 0) OF std_logic_vector(7 DOWNTO 0);
>
> > > Since your read and write pointers are std_logic_vectors, they cannot
> > > be used for indexing into and array. Convert them to integers using
> > > the functions in numeric_std package like so
>
> > > DataOut <= queue(to_integer(ReadPointer));
>
> > > and
>
> > > queue(to_integer(WritePointer)) <= DataIn;
>
> > > Hope this helps,
> > > Sudheendra Kadri- Hide quoted text -
>
> > > - Show quoted text -
>
> > Shouldnt the array be multidimensional? Isnt the array you defined one
> > dimensional?- Hide quoted text -
>
> > - Show quoted text -
>
> I am getting the following error message
> No feasible entries for subprogram "to_integer".
>
> I HAVE INCLUDED NUMERIC_STD package as follows
>
> LIBRARY IEEE;
> USE IEEE.std_logic_1164.ALL;
> USE IEEE.std_logic_unsigned.ALL;
> USE IEEE.numeric_std.ALL;
>
> It also comlained about target of signal assignment is not a signal.
> So, I defined q_queue of type queue(array) and that was solved.


Take a look at this for the conversion problem

http://dz.ee.ethz.ch/support/ic/vhdl/vhdlsources.en.html

In a fifo you only need a single dimensional array of
std_logic_vectors. If the fifo is bit addressable then you could call
this declaration a multidimensional array.

-Sudheendra Kadri
Reply by RCIngham ●December 18, 20072007-12-18
>On Dec 17, 4:39 pm, Anuja <thakkar.an...@gmail.com> wrote:
>> On Dec 17, 4:30 pm, sudhi <sudhi.ka...@gmail.com> wrote:


 <snip />


>>
>> > Since your read and write pointers are std_logic_vectors, they

cannot

>> > be used for indexing into and array. Convert them to integers using
>> > the functions in numeric_std package like so
>>
>> > DataOut <= queue(to_integer(ReadPointer));
>>
>> > and
>>
>> > queue(to_integer(WritePointer)) <= DataIn;
>>
>> > Hope this helps,
>> > Sudheendra Kadri- Hide quoted text -
>>
>> > - Show quoted text -
>>
>> Shouldnt the array be multidimensional? Isnt the array you defined one
>> dimensional?- Hide quoted text -
>>
>> - Show quoted text -
>
>I am getting the following error message
>No feasible entries for subprogram "to_integer".
>
>I HAVE INCLUDED NUMERIC_STD package as follows
>
>LIBRARY IEEE;
>USE IEEE.std_logic_1164.ALL;
>USE IEEE.std_logic_unsigned.ALL;
>USE IEEE.numeric_std.ALL;
>
>It also comlained about target of signal assignment is not a signal.
>So, I defined q_queue of type queue(array) and that was solved.
>
>


You do not need "USE IEEE.std_logic_unsigned.ALL;" Instead do a cast to
type 'unsigned'...

DataOut <= queue(to_integer(unsigned(ReadPointer)));

queue(to_integer(unsigned(WritePointer))) <= DataIn;
Reply by comp.arch.fpga ●December 18, 20072007-12-18
On 18 Dez., 10:31, "RCIngham" <robert.ing...@gmail.com> wrote:

> >On Dec 17, 4:39 pm, Anuja <thakkar.an...@gmail.com> wrote:
> >> On Dec 17, 4:30 pm, sudhi <sudhi.ka...@gmail.com> wrote:
>
>  <snip />
>
>
>
>
>
>
>
> >> > Since your read and write pointers are std_logic_vectors, they
> cannot
> >> > be used for indexing into and array. Convert them to integers using
> >> > the functions in numeric_std package like so
>
> >> > DataOut <= queue(to_integer(ReadPointer));
>
> >> > and
>
> >> > queue(to_integer(WritePointer)) <= DataIn;
>
> >> > Hope this helps,
> >> > Sudheendra Kadri- Hide quoted text -
>
> >> > - Show quoted text -
>
> >> Shouldnt the array be multidimensional? Isnt the array you defined one
> >> dimensional?- Hide quoted text -
>
> >> - Show quoted text -
>
> >I am getting the following error message
> >No feasible entries for subprogram "to_integer".
>
> >I HAVE INCLUDED NUMERIC_STD package as follows
>
> >LIBRARY IEEE;
> >USE IEEE.std_logic_1164.ALL;
> >USE IEEE.std_logic_unsigned.ALL;
> >USE IEEE.numeric_std.ALL;
>
> >It also comlained about target of signal assignment is not a signal.
> >So, I defined q_queue of type queue(array) and that was solved.
>
> You do not need "USE IEEE.std_logic_unsigned.ALL;"

In fact, including both is dangerous.
Also, std_logic_unisgned is deprecated.


> Instead do a cast to type 'unsigned'...
> DataOut <= queue(to_integer(unsigned(ReadPointer)));
> queue(to_integer(unsigned(WritePointer))) <= DataIn;


Or even better, declare read pointer to be an integer to begin with:
signal ReadPointer : integer range 0 to RANGE-1 := 0;
This avoids both casts.

Kolja Sulimma
Reply by Anuja ●December 18, 20072007-12-18
On Dec 18, 4:57 am, "comp.arch.fpga" <ksuli...@googlemail.com> wrote:

> On 18 Dez., 10:31, "RCIngham" <robert.ing...@gmail.com> wrote:
>
>
>
> > >On Dec 17, 4:39 pm, Anuja <thakkar.an...@gmail.com> wrote:
> > >> On Dec 17, 4:30 pm, sudhi <sudhi.ka...@gmail.com> wrote:
>
> >  <snip />
>
> > >> > Since your read and write pointers are std_logic_vectors, they
> > cannot
> > >> > be used for indexing into and array. Convert them to integers using
> > >> > the functions in numeric_std package like so
>
> > >> > DataOut <= queue(to_integer(ReadPointer));
>
> > >> > and
>
> > >> > queue(to_integer(WritePointer)) <= DataIn;
>
> > >> > Hope this helps,
> > >> > Sudheendra Kadri- Hide quoted text -
>
> > >> > - Show quoted text -
>
> > >> Shouldnt the array be multidimensional? Isnt the array you defined one
> > >> dimensional?- Hide quoted text -
>
> > >> - Show quoted text -
>
> > >I am getting the following error message
> > >No feasible entries for subprogram "to_integer".
>
> > >I HAVE INCLUDED NUMERIC_STD package as follows
>
> > >LIBRARY IEEE;
> > >USE IEEE.std_logic_1164.ALL;
> > >USE IEEE.std_logic_unsigned.ALL;
> > >USE IEEE.numeric_std.ALL;
>
> > >It also comlained about target of signal assignment is not a signal.
> > >So, I defined q_queue of type queue(array) and that was solved.
>
> > You do not need "USE IEEE.std_logic_unsigned.ALL;"
>
> In fact, including both is dangerous.
> Also, std_logic_unisgned is deprecated.
>
> > Instead do a cast to type 'unsigned'...
> > DataOut <= queue(to_integer(unsigned(ReadPointer)));
> > queue(to_integer(unsigned(WritePointer))) <= DataIn;
>
> Or even better, declare read pointer to be an integer to begin with:
> signal ReadPointer : integer range 0 to RANGE-1 := 0;
> This avoids both casts.
>
> Kolja Sulimma- Hide quoted text -
>
> - Show quoted text -


My problem was solved by using the package
IEEE.std_logic_unsigned.ALL; and I used the function conv_integer
which directly converts the std_logic_vector to integer. In this case
i do not have to convert the vector to unsigned.

Thank you all for your help

Anuja
Reply by RCIngham ●December 18, 20072007-12-18
  <snip />


>
>My problem was solved by using the package
>IEEE.std_logic_unsigned.ALL; and I used the function conv_integer
>which directly converts the std_logic_vector to integer. In this case
>i do not have to convert the vector to unsigned.
>
>Thank you all for your help
>
>Anuja
>


If you ever go on a VHDL course, I am sure that you will be told that use
of the 'std_logic_arith', 'std_logic_signed', 'std_logic_unsigned'
packages is DEPRECATED, and that you should only use the IEEE Standard
1076.3-1997 'numeric_std' (or 'numeric_bit' if not using 9-level logic)
package. I strongly advise you to get into this good habit now.
Reply by Anuja ●December 18, 20072007-12-18
On Dec 18, 8:50 am, "RCIngham" <robert.ing...@gmail.com> wrote:

>   <snip />
>
>
>
> >My problem was solved by using the package
> >IEEE.std_logic_unsigned.ALL; and I used the function conv_integer
> >which directly converts the std_logic_vector to integer. In this case
> >i do not have to convert the vector to unsigned.
>
> >Thank you all for your help
>
> >Anuja
>
> If you ever go on a VHDL course, I am sure that you will be told that use
> of the 'std_logic_arith', 'std_logic_signed', 'std_logic_unsigned'
> packages is DEPRECATED, and that you should only use the IEEE Standard
> 1076.3-1997 'numeric_std' (or 'numeric_bit' if not using 9-level logic)
> package. I strongly advise you to get into this good habit now.


Thank you very much for your advise