FPGA Project Support

Dear Sir,

My full project title is to create a dot product of 'n'
numbers(a0*b0+a1*b1+....+aN*bN) using MicroBlaze.

I want a VHDL code for scalar dot product of n inputs. It should be
added as custom IP (Intellectual Property) in to the hardware
peripheral and interfaced with MicroBlaze. The target board is
Vertex2Pro (maximum clock frequency 100 MHZ) and the same can be seen
in the website given below.

http://wiki.ittc.ku.edu/ittc/Eecs388

I have to use MicroBlaze (Softcore) to pass the dot products values to
the custom IP (Hardcore).

No calculation should be done on the MicroBlaze (softcore). The
calculation should be done on the custom IP (hard core).

Following are the Phases involved.

Phase1: Creation of VHDL code for N input dot product

Phase2: Addition of custom IP (VHDL code of scalar dot product) and
interface it with using MicroBlaze

Phase3: Download into FPGA and result of the dot product is seen in
the hyper terminal because the FPGA Board is interfaced with Computer
via RS232 Serial Cable.

The above Project is to be worked with

Xilinx EDK 9.1i for implementation in FPGA and Xilinx ISE 9.1i for
simulating the custom IP generated.

Kindly let me know whether you can provide On-Line Support and provide
solution for the above Project.

Regards

S. Arunkumar

BALAS009 wrote:
> Dear Sir,
> 
> My full project title is to create a dot product of 'n'
> numbers(a0*b0+a1*b1+....+aN*bN) using MicroBlaze.
> 
> I want a VHDL code for scalar dot product of n inputs. It should be
> added as custom IP (Intellectual Property) in to the hardware
> peripheral and interfaced with MicroBlaze. The target board is
> Vertex2Pro (maximum clock frequency 100 MHZ) and the same can be seen
> in the website given below.
> 
> http://wiki.ittc.ku.edu/ittc/Eecs388
> 
> I have to use MicroBlaze (Softcore) to pass the dot products values to
> the custom IP (Hardcore).
> 
> No calculation should be done on the MicroBlaze (softcore). The
> calculation should be done on the custom IP (hard core).
> 
> Following are the Phases involved.
> 
> Phase1: Creation of VHDL code for N input dot product
> 
> Phase2: Addition of custom IP (VHDL code of scalar dot product) and
> interface it with using MicroBlaze
> 
> Phase3: Download into FPGA and result of the dot product is seen in
> the hyper terminal because the FPGA Board is interfaced with Computer
> via RS232 Serial Cable.
> 
> The above Project is to be worked with
> 
> Xilinx EDK 9.1i for implementation in FPGA and Xilinx ISE 9.1i for
> simulating the custom IP generated.
> 
> Kindly let me know whether you can provide On-Line Support and provide
> solution for the above Project.
> 
> Regards
> 
> S. Arunkumar

This appears to be the absolutely most blatant "Do my work for me!" 
demand I've seen so far.  You want a SOLUTION?!  I won't repeat the 
phrase going through my head right now.

You might garner some support if you give some indication that you're 
doing your own work.  We - as a profession - do NOT need new engineers 
graduating with this kind of attitude toward assignments.

Withdraw now and go into business school; those are the kinds of people 
that get others to do their work for them.

If you want assistance, please use the university resources and leave us 
otherwise generous professionals alone.

Merry Christmas.

My car needs an oil change.
And all the windows in my house need a thorough wash.
When can you come by and do that ? For free, of course...
Peter Alfke

On Dec 24, 6:24=A0am, BALAS009 <BALAS...@gmail.com> wrote:
> Dear Sir,
>
> My full project title is to create a dot product of 'n'
> numbers(a0*b0+a1*b1+....+aN*bN) using MicroBlaze.
>
> I want a VHDL code for scalar dot product of n inputs. It should be
> added as custom IP (Intellectual Property) in to the hardware
> peripheral and interfaced with MicroBlaze. The target board is
> Vertex2Pro (maximum clock frequency 100 MHZ) and the same can be seen
> in the website given below.
>
> http://wiki.ittc.ku.edu/ittc/Eecs388
>
> I have to use MicroBlaze (Softcore) to pass the dot products values to
> the custom IP (Hardcore).
>
> No calculation should be done on the MicroBlaze (softcore). The
> calculation should be done on the custom IP (hard core).
>
> Following are the Phases involved.
>
> Phase1: Creation of VHDL code for N input dot product
>
> Phase2: Addition of custom IP (VHDL code of scalar dot product) and
> interface it with using MicroBlaze
>
> Phase3: Download into FPGA and result of the dot product is seen in
> the hyper terminal because the FPGA Board is interfaced with Computer
> via RS232 Serial Cable.
>
> The above Project is to be worked with
>
> Xilinx EDK 9.1i for implementation in FPGA and Xilinx ISE 9.1i for
> simulating the custom IP generated.
>
> Kindly let me know whether you can provide On-Line Support and provide
> solution for the above Project.
>
> Regards
>
> S. Arunkumar

John_H <newsgroup@johnhandwork.com> wrote:

>BALAS009 wrote:
>> Dear Sir,
>> 
>> My full project title is to create a dot product of 'n'
>> numbers(a0*b0+a1*b1+....+aN*bN) using MicroBlaze.
>> 
>> I want a VHDL code for scalar dot product of n inputs. It should be
>> added as custom IP (Intellectual Property) in to the hardware
>> peripheral and interfaced with MicroBlaze. The target board is
>> Vertex2Pro (maximum clock frequency 100 MHZ) and the same can be seen
>> in the website given below.
>> 
>> http://wiki.ittc.ku.edu/ittc/Eecs388
>> 
>> The above Project is to be worked with
>> 
>> Xilinx EDK 9.1i for implementation in FPGA and Xilinx ISE 9.1i for
>> simulating the custom IP generated.
>> 
>> Kindly let me know whether you can provide On-Line Support and provide
>> solution for the above Project.
>> 
>> Regards
>> 
>> S. Arunkumar
>
>This appears to be the absolutely most blatant "Do my work for me!" 
>demand I've seen so far.  You want a SOLUTION?!  I won't repeat the 
>phrase going through my head right now.

Hint, some people pay to get their homework done. Works great since
they are likely to become a regular customer...

-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

GREETINGS AND FELICITATIONS, MR G'MAIL - 

I AM PROUD TO PRESENT MYSELF TO YOU AS NABALU "SKIPPY" UMBEKE,
MINISTER OF DESIGN FOR THE EXALTED FEDERAL REPUBLIC OF NIGERIA IN
ABUJA.  IT IS FOR ME TO OFFER YOU A FINDING ARISING FROM UNUSUAL
CIRCUMSTANCES.  AN ENGINEER WORKING FOR OUR MINISTRY RECENTLY DECEASED
HIMSELF, LEAVING IN HIS WAKE AN FPGA DESIGN FOR WHAT WE CALL IT SCALAR
DOT PRODUCT.  IN HAPPY HAPPENSTANCE, WE ALSO HAVE NOT PAID FOR THIS
DESIGN APPURTENANCE, LEAVING OUR OFFICES WITH A DUE PAYMENT OF
$24,500,000 (TWENTY FOUR POINT FIVE MILLION DOLLARS).

MR. G'MAIL, WOULD YOU BE WILLING TO DO US CONSIDERABLE SERVICE AND
TAKE DESIGN AND EXCESS DOLLARS OFF OUR TABLE? WE CAN EASY TRANSFER
BOTH TO YOU WITH IMMEDIACY IF YOU WOULD ONLY GIVE TO US YOUR BANK
ACCOUNT NUMBERS, SOCIAL SECURITY NUMBER, AND ANY OTHER SUCH PRIVATE
INFORMATIONS THAT YOU WOULD BE RELUCTANT TO EMIT TO ANYONE OTHER THAN
A MINISTER OF DESIGN IN A FARAWAY LAND.  AS SOON AS I USURP THIS
INFORMATION FROM YOU, I WILL HASTILY TRANSFER TO YOU THE MONIES AND
THE DESIGN BOTH.  AS A SIGN OF OUR FAITH AND GOODWILL IN THIS
BURGEONING BUSINESS RELATIONSHIP, WE WILL SEND TO YOU ALSO A DESIGN
FOR A MOST EXCELLENT TRAFFIC LIGHT CONTROLLER.

YOURS IN THE EPITOME OF HUMBLE SINCERITY,
NABULU UMBEKE
MINISTER OF DESIGN

>This appears to be the absolutely most blatant "Do my work for me!" 
>demand I've seen so far.  You want a SOLUTION?!  I won't repeat the 
>phrase going through my head right now.

I understood him to be asking for a commercial tender.

In article <odqdnUQPmoYvlO3anZ2dnUVZ_t2inZ2d@comcast.com>,
John_H  <newsgroup@johnhandwork.com> wrote:
>BALAS009 wrote:
>> Dear Sir,
>> 
>> My full project title is to create a dot product of 'n'
>> numbers(a0*b0+a1*b1+....+aN*bN) using MicroBlaze.
>> 
>> I want a VHDL code for scalar dot product of n inputs. It should be
>> added as custom IP (Intellectual Property) in to the hardware
>> peripheral and interfaced with MicroBlaze. The target board is
>> Vertex2Pro (maximum clock frequency 100 MHZ) and the same can be seen
>> in the website given below.
>> 
>> http://wiki.ittc.ku.edu/ittc/Eecs388
>> 
>
>This appears to be the absolutely most blatant "Do my work for me!" 
>demand I've seen so far.  You want a SOLUTION?!  I won't repeat the 
>phrase going through my head right now.
>
>You might garner some support if you give some indication that you're 
>doing your own work.  We - as a profession - do NOT need new engineers 
>graduating with this kind of attitude toward assignments.
>
>Withdraw now and go into business school; those are the kinds of people 
>that get others to do their work for them.
>
>If you want assistance, please use the university resources and leave us 
>otherwise generous professionals alone.
>
>Merry Christmas.

I thought the the link was intersting. As a graduate student in ECE,
I've taken every course my school offers related to configurable logic
and haven't had anything this interesting offered. Not one class has
included taking a design to hardware, I've had to do that on my own. The
designs required for the classes have also been very small, bordering on
trivial in the most challenging cases.

Oh, well, that's a cool thing about FPGAs - it's pretty easy to do it
on your own. It's just that I could justify more time on it if I were
getting credit...

Good job, University of Kansas!

Rick

rickc (a) rdrop com

Bob Perlman wrote:
> GREETINGS AND FELICITATIONS, MR G'MAIL - 
> 
> I AM PROUD TO PRESENT MYSELF TO YOU AS NABALU "SKIPPY" UMBEKE,
> MINISTER OF DESIGN FOR THE EXALTED FEDERAL REPUBLIC OF NIGERIA IN
> ABUJA.  IT IS FOR ME TO OFFER YOU A FINDING ARISING FROM UNUSUAL
> CIRCUMSTANCES.  AN ENGINEER WORKING FOR OUR MINISTRY RECENTLY DECEASED
> HIMSELF, LEAVING IN HIS WAKE AN FPGA DESIGN FOR WHAT WE CALL IT SCALAR
> DOT PRODUCT.  IN HAPPY HAPPENSTANCE, WE ALSO HAVE NOT PAID FOR THIS
> DESIGN APPURTENANCE, LEAVING OUR OFFICES WITH A DUE PAYMENT OF
> $24,500,000 (TWENTY FOUR POINT FIVE MILLION DOLLARS).
> 
> MR. G'MAIL, WOULD YOU BE WILLING TO DO US CONSIDERABLE SERVICE AND
> TAKE DESIGN AND EXCESS DOLLARS OFF OUR TABLE? WE CAN EASY TRANSFER
> BOTH TO YOU WITH IMMEDIACY IF YOU WOULD ONLY GIVE TO US YOUR BANK
> ACCOUNT NUMBERS, SOCIAL SECURITY NUMBER, AND ANY OTHER SUCH PRIVATE
> INFORMATIONS THAT YOU WOULD BE RELUCTANT TO EMIT TO ANYONE OTHER THAN
> A MINISTER OF DESIGN IN A FARAWAY LAND.  AS SOON AS I USURP THIS
> INFORMATION FROM YOU, I WILL HASTILY TRANSFER TO YOU THE MONIES AND
> THE DESIGN BOTH.  AS A SIGN OF OUR FAITH AND GOODWILL IN THIS
> BURGEONING BUSINESS RELATIONSHIP, WE WILL SEND TO YOU ALSO A DESIGN
> FOR A MOST EXCELLENT TRAFFIC LIGHT CONTROLLER.
> 
> YOURS IN THE EPITOME OF HUMBLE SINCERITY,
> NABULU UMBEKE
> MINISTER OF DESIGN

Mr. Umbeke,

I'm sure the original poster thanks you for your kind offer of 
assistance. As it happens, I also have come into possession of much 
knowledge through my years of experience. Perhaps it would be possible 
for us to coagulate our knowledge to help this poor unfortunate student. 
I would be glad, nay enthralled, to share my portion of a useful design 
for a mere 30% of the total moneys involved.

Yours, to the attainment of higher knowledge,

RB

P.S. Great post, Bob. Sorry I can't do it justice.

BALAS009 wrote:
> Dear Sir,
> 
> My full project title is to create a dot product of 'n'
> numbers(a0*b0+a1*b1+....+aN*bN) using MicroBlaze.
> 
> I want a VHDL code for scalar dot product of n inputs. It should be
> added as custom IP (Intellectual Property) in to the hardware
> peripheral and interfaced with MicroBlaze. The target board is
> Vertex2Pro (maximum clock frequency 100 MHZ) and the same can be seen
> in the website given below.
> 
> http://wiki.ittc.ku.edu/ittc/Eecs388
> 
> I have to use MicroBlaze (Softcore) to pass the dot products values to
> the custom IP (Hardcore).
> 
> No calculation should be done on the MicroBlaze (softcore). The
> calculation should be done on the custom IP (hard core).
> 
> Following are the Phases involved.
> 
> Phase1: Creation of VHDL code for N input dot product
> 
> Phase2: Addition of custom IP (VHDL code of scalar dot product) and
> interface it with using MicroBlaze
> 
> Phase3: Download into FPGA and result of the dot product is seen in
> the hyper terminal because the FPGA Board is interfaced with Computer
> via RS232 Serial Cable.
> 
> The above Project is to be worked with
> 
> Xilinx EDK 9.1i for implementation in FPGA and Xilinx ISE 9.1i for
> simulating the custom IP generated.
> 
> Kindly let me know whether you can provide On-Line Support and provide
> solution for the above Project.
> 
> Regards
> 
> S. Arunkumar

I'm sure Dr. Andrews would love to hear about this.

RB

> Regards
> S. Arunkumar

	Should you wish to get a complete, working design, please answer  
privately so I can give you my Paypal ID.

	Anyway, here is how I would do it. I will provide two solutions.

	Solution #1 : "the works". Your teacher will bow before your m4d skillZ.

	"dot product" core is an OPB master.
	Microblaze writes into "dot product" core's registers, information about  
where to grab the data in memory (vector 1 address, vector 2 address,  
vector length). "dot product" core acts as an OPB DMA master and  
burst-reads vector data, computes dot product, and wakes Microblaze up  
with an interrupt when it's done. Microblaze will then read result in "dot  
product" core's register. For added points, add provision for partitioned  
convolution.

	Solution #2 : damn, get this over with.
	Vector data is stored in opb_bram memory. Memory is dual port, so one  
port is connected to OPB via standard Xilinx opb_bram core. Standard  
Xilinx central_dma core is used to copy vector data from SDRAM into the  
dedicated BRAM. Microblaze writes into "dot product" core's registers,  
information about where to grab the data in BRAM (vector 1 address, vector  
2 address, vector length). "dot product" core hits BRAM and reads vector  
data, computes dot product, and wakes Microblaze up with an interrupt when  
it's done. Microblaze will then read result in "dot product" core's  
register.