spartan 3e JTAG programming

Hi guys

I have two spartan 3e's and a coolrunner in a single JTAG chain.

If I program either FPGA from power up its outputs do not drive, but I
can read the JTAG user register and it has the value that I set from
"generate programming file" so the binary is in the FPGA but the IO
doesn't get driven, presumably the "enable outputs" state in the
startup sequence never occurs.

When I program the other FPGA it works correctly, but the first still
does not drive.

I then reprogram the first FPGA and it now works correctly as well.

prog_b is driven high throughout the above.
The two done's are connected together and pulled up to 2v5.
the init_b's are connected together and pulled up to 3v3 (the bank IO
voltage)

I haven't seen any activity on the done or init_b signals.

Could someone please point me to which signal from the unprogrammed
fpga stops the first FPGA from driving out forever.

thanks and regards

Katherine

Katherine,

Often the start-up sequence requires a few extra clocks to complete.
Check to see if you are sending enough nulls after the end of the bitstream.

http://www.xilinx.com/support/documentation/user_guides/ug332.pdf

page 238

The startup sequence requires eight more clocks to complete, so if you
stop the TCK on the JTAG, then you have loaded the bitstream, but have
not clocked through the startup sequence state machine.

Austin