Hi all !
I simulate a simple design (synchronus RESET/LOAD 8-bits counter) with
iverilog and testbench associated. Waveforms with gtkwave looks good.
I have been trying to synthetise a simple 8bit counter within WebPack ISE
9.2 edition.
The "Translate" phase failed :
....
Writing NGD file "counter.ngd" ...
Writing NGDBUILD log file "counter.bld"...
NGDBUILD done.
Process "Translate" failed
...
What's wrong with this ?
PS :
/* ------------ SIMPLE 8 BITS Synchronous Counter -------------*/
`timescale 1ns / 1ps
module counter(in, out, clk, reset, load);
input [7:0] in;
input clk;
input reset;
input load;
output reg[7:0] out;
/* Chargement synchrone par load */
always @(posedge clk)
begin
out<=out+1;
if (reset==1)
out[7:0] <= 0;
else if(load==1)
out[7:0] <= in[7:0];
end
endmodule
Here the test_bench associated
module test();
reg [7:0] bin ;
wire [7:0] bout ;
reg clk, reset, load; // wire s, cout;
counter counter_en_test(bin, bout, clk, reset, load);
initial
begin
bin = 4'b00010111;
clk = 0;
load = 0;
reset = 0;
#5;
clk = 1;
load = 1;
#5;
clk = 0;
load=0;
#5;
clk = 1;
#5;
clk = 0;
#5;
clk = 1;
#5;
clk = 0;
load = 1;
#5;
clk = 1;
#5;
clk = 0;
#5;
clk = 1;
end // initial begin
initial
begin
$dumpfile ("counter.vcd");
$dumpvars;
end
initial
begin
$display("\t\ttime,\tclk,\tin,\tout,\treset,\tload");
$monitor("%d \t%d \t%d \t%b \t%b \t%b",$time, bin, bout, clk, reset, load);
end
endmodule // test
--
HBV
WebPack on GNU/Linux
Started by ●January 3, 2008
Reply by ●January 3, 20082008-01-03
Habib Bouaziz-Viallet wrote:> Hi all ! > > I simulate a simple design (synchronus RESET/LOAD 8-bits counter) with > iverilog and testbench associated. Waveforms with gtkwave looks good. > > I have been trying to synthetise a simple 8bit counter within WebPack ISE > 9.2 edition. > > The "Translate" phase failed : > .... > Writing NGD file "counter.ngd" ... > Writing NGDBUILD log file "counter.bld"... > NGDBUILD done. > Process "Translate" failed > > ... > > What's wrong with this ?Did it give you any specific errors ? (click on 'Errors' tab at the bottom).> > > PS : > /* ------------ SIMPLE 8 BITS Synchronous Counter -------------*/ > `timescale 1ns / 1ps > module counter(in, out, clk, reset, load); > input [7:0] in; > input clk; > input reset; > input load; > output reg[7:0] out; > > /* Chargement synchrone par load */ > always @(posedge clk) > begin > out<=out+1; > if (reset==1) > out[7:0] <= 0; > else if(load==1) > out[7:0] <= in[7:0]; > endYou're doing two assignments to 'out' in the same clock cycle. Try: always @(posedge clk) begin if (reset==1) out[7:0] <= 0; else if(load==1) out[7:0] <= in[7:0]; else out<=out+1; end> > endmodule > > Here the test_bench associated > > > module test(); > > reg [7:0] bin ; > wire [7:0] bout ; > reg clk, reset, load; // wire s, cout; > > counter counter_en_test(bin, bout, clk, reset, load); > > initial > begin > > bin = 4'b00010111; > clk = 0; > load = 0; > reset = 0; > > #5; > clk = 1; > load = 1; > > > #5; > clk = 0; > load=0; > > #5; > clk = 1; > > #5; > clk = 0; > > #5; > clk = 1; > > #5; > clk = 0; > load = 1; > > #5; > clk = 1; > > #5; > clk = 0; > > #5; > clk = 1; > > > end // initial begin > > initial > begin > $dumpfile ("counter.vcd"); > $dumpvars; > end > > initial > begin > $display("\t\ttime,\tclk,\tin,\tout,\treset,\tload"); > $monitor("%d \t%d \t%d \t%b \t%b \t%b",$time, bin, bout, clk, reset, load); > end > > endmodule // test > > >
Reply by ●January 3, 20082008-01-03
Le Thu, 03 Jan 2008 15:02:31 +0100, Arlet Ottens a écrit:> Habib Bouaziz-Viallet wrote: >> Hi all ! >> >> I simulate a simple design (synchronus RESET/LOAD 8-bits counter) with >> iverilog and testbench associated. Waveforms with gtkwave looks good. >> >> I have been trying to synthetise a simple 8bit counter within WebPack ISE >> 9.2 edition. >> >> The "Translate" phase failed : >> .... >> Writing NGD file "counter.ngd" ... >> Writing NGDBUILD log file "counter.bld"... >> NGDBUILD done. >> Process "Translate" failed >> >> ... >> >> What's wrong with this ? > > Did it give you any specific errors ? (click on 'Errors' tab at the bottom). >No. But i have WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology. (In Warnings TAB)> > >> >> PS : >> /* ------------ SIMPLE 8 BITS Synchronous Counter -------------*/ >> `timescale 1ns / 1ps >> module counter(in, out, clk, reset, load); >> input [7:0] in; >> input clk; >> input reset; >> input load; >> output reg[7:0] out; >> >> /* Chargement synchrone par load */ >> always @(posedge clk) >> begin >> out<=out+1; >> if (reset==1) >> out[7:0] <= 0; >> else if(load==1) >> out[7:0] <= in[7:0]; >> end > > You're doing two assignments to 'out' in the same clock cycle.That's right but i'm not sur that this is an issue in that case. I'm learning Verilog at the moment. Thanks.> > Try: > > always @(posedge clk) > begin > if (reset==1) > out[7:0] <= 0; > else if(load==1) > out[7:0] <= in[7:0]; > else > out<=out+1; > end > > > >> endmodule >> >> Here the test_bench associated >> >> >> module test(); >> >> reg [7:0] bin ; >> wire [7:0] bout ; >> reg clk, reset, load; // wire s, cout; >> >> counter counter_en_test(bin, bout, clk, reset, load); >> >> initial >> begin >> >> bin = 4'b00010111; >> clk = 0; >> load = 0; >> reset = 0; >> >> #5; >> clk = 1; >> load = 1; >> >> >> #5; >> clk = 0; >> load=0; >> >> #5; >> clk = 1; >> >> #5; >> clk = 0; >> >> #5; >> clk = 1; >> >> #5; >> clk = 0; >> load = 1; >> >> #5; >> clk = 1; >> >> #5; >> clk = 0; >> >> #5; >> clk = 1; >> >> >> end // initial begin >> >> initial >> begin >> $dumpfile ("counter.vcd"); >> $dumpvars; >> end >> >> initial >> begin >> $display("\t\ttime,\tclk,\tin,\tout,\treset,\tload"); $monitor("%d >> \t%d \t%d \t%b \t%b \t%b",$time, bin, bout, clk, reset, load); >> end >> >> endmodule // test >> >> >>-- HBV
Reply by ●January 3, 20082008-01-03
Habib Bouaziz-Viallet wrote:> Le Thu, 03 Jan 2008 15:02:31 +0100, Arlet Ottens a écrit: > >> Habib Bouaziz-Viallet wrote: >>> Hi all ! >>> >>> I simulate a simple design (synchronus RESET/LOAD 8-bits counter) with >>> iverilog and testbench associated. Waveforms with gtkwave looks good. >>> >>> I have been trying to synthetise a simple 8bit counter within WebPack ISE >>> 9.2 edition. >>> >>> The "Translate" phase failed : >>> .... >>> Writing NGD file "counter.ngd" ... >>> Writing NGDBUILD log file "counter.bld"... >>> NGDBUILD done. >>> Process "Translate" failed >>> >>> ... >>> >>> What's wrong with this ? >> Did it give you any specific errors ? (click on 'Errors' tab at the bottom). >> > No. But i have WARNING:Xst:2734 - Property "use_dsp48" is not applicable > for this technology. (In Warnings TAB) >> >>> PS : >>> /* ------------ SIMPLE 8 BITS Synchronous Counter -------------*/ >>> `timescale 1ns / 1ps >>> module counter(in, out, clk, reset, load); >>> input [7:0] in; >>> input clk; >>> input reset; >>> input load; >>> output reg[7:0] out; >>> >>> /* Chargement synchrone par load */ >>> always @(posedge clk) >>> begin >>> out<=out+1; >>> if (reset==1) >>> out[7:0] <= 0; >>> else if(load==1) >>> out[7:0] <= in[7:0]; >>> end >> You're doing two assignments to 'out' in the same clock cycle. > That's right but i'm not sur that this is an issue in that case. I'm > learning Verilog at the moment. Thanks. >> Try: >> >> always @(posedge clk) >> begin >> if (reset==1) >> out[7:0] <= 0; >> else if(load==1) >> out[7:0] <= in[7:0]; >> else >> out<=out+1; >> end >>I tried this counter module in ISE Webpack 9.2 in Linux, and it builds fine. The test bench contains constructs that aren't synthesizable, such as the delays, $display() calls, and the fact that it doesn't have any I/O signals.>> >> >>> endmodule >>> >>> Here the test_bench associated >>> >>> >>> module test(); >>> >>> reg [7:0] bin ; >>> wire [7:0] bout ; >>> reg clk, reset, load; // wire s, cout; >>> >>> counter counter_en_test(bin, bout, clk, reset, load); >>> >>> initial >>> begin >>> >>> bin = 4'b00010111; >>> clk = 0; >>> load = 0; >>> reset = 0; >>> >>> #5; >>> clk = 1; >>> load = 1; >>> >>> >>> #5; >>> clk = 0; >>> load=0; >>> >>> #5; >>> clk = 1; >>> >>> #5; >>> clk = 0; >>> >>> #5; >>> clk = 1; >>> >>> #5; >>> clk = 0; >>> load = 1; >>> >>> #5; >>> clk = 1; >>> >>> #5; >>> clk = 0; >>> >>> #5; >>> clk = 1; >>> >>> >>> end // initial begin >>> >>> initial >>> begin >>> $dumpfile ("counter.vcd"); >>> $dumpvars; >>> end >>> >>> initial >>> begin >>> $display("\t\ttime,\tclk,\tin,\tout,\treset,\tload"); $monitor("%d >>> \t%d \t%d \t%b \t%b \t%b",$time, bin, bout, clk, reset, load); >>> end >>> >>> endmodule // test >>> >>> >>> > > >
Reply by ●January 3, 20082008-01-03
Le Thu, 03 Jan 2008 15:31:26 +0100, Arlet Ottens a écrit:> Habib Bouaziz-Viallet wrote: > >> Le Thu, 03 Jan 2008 15:02:31 +0100, Arlet Ottens a écrit: >> >>> Habib Bouaziz-Viallet wrote: >>>> Hi all ! >>>> >>>> I simulate a simple design (synchronus RESET/LOAD 8-bits counter) with >>>> iverilog and testbench associated. Waveforms with gtkwave looks good. >>>> >>>> I have been trying to synthetise a simple 8bit counter within WebPack ISE >>>> 9.2 edition. >>>> >>>> The "Translate" phase failed : >>>> .... >>>> Writing NGD file "counter.ngd" ... >>>> Writing NGDBUILD log file "counter.bld"... >>>> NGDBUILD done. >>>> Process "Translate" failed >>>> >>>> ... >>>> >>>> What's wrong with this ? >>> Did it give you any specific errors ? (click on 'Errors' tab at the bottom). >>> >> No. But i have WARNING:Xst:2734 - Property "use_dsp48" is not applicable >> for this technology. (In Warnings TAB) >>> >>>> PS : >>>> /* ------------ SIMPLE 8 BITS Synchronous Counter -------------*/ >>>> `timescale 1ns / 1ps >>>> module counter(in, out, clk, reset, load); >>>> input [7:0] in; >>>> input clk; >>>> input reset; >>>> input load; >>>> output reg[7:0] out; >>>> >>>> /* Chargement synchrone par load */ >>>> always @(posedge clk) >>>> begin >>>> out<=out+1; >>>> if (reset==1) >>>> out[7:0] <= 0; >>>> else if(load==1) >>>> out[7:0] <= in[7:0]; >>>> end >>> You're doing two assignments to 'out' in the same clock cycle. >> That's right but i'm not sur that this is an issue in that case. I'm >> learning Verilog at the moment. Thanks. >>> Try: >>> >>> always @(posedge clk) >>> begin >>> if (reset==1) >>> out[7:0] <= 0; >>> else if(load==1) >>> out[7:0] <= in[7:0]; >>> else >>> out<=out+1; >>> end >>> > > I tried this counter module in ISE Webpack 9.2 in Linux, and it builds > fine.waouh ! Is it a GNU/Linux ditrib pb ? I'm running debian GNU/Linux.> > The test bench contains constructs that aren't synthesizable, such as > the delays, $display() calls, and the fact that it doesn't have any I/O > signals.That's right. the test bench is here only for getting readeable results with iverilog(or cver) and gtkwave> > > >>>> endmodule >>>> >>>> Here the test_bench associated >>>> >>>> >>>> module test(); >>>> >>>> reg [7:0] bin ; >>>> wire [7:0] bout ; >>>> reg clk, reset, load; // wire s, cout; >>>> >>>> counter counter_en_test(bin, bout, clk, reset, load); >>>> >>>> initial >>>> begin >>>> >>>> bin = 4'b00010111; >>>> clk = 0; >>>> load = 0; >>>> reset = 0; >>>> >>>> #5; >>>> clk = 1; >>>> load = 1; >>>> >>>> >>>> #5; >>>> clk = 0; >>>> load=0; >>>> >>>> #5; >>>> clk = 1; >>>> >>>> #5; >>>> clk = 0; >>>> >>>> #5; >>>> clk = 1; >>>> >>>> #5; >>>> clk = 0; >>>> load = 1; >>>> >>>> #5; >>>> clk = 1; >>>> >>>> #5; >>>> clk = 0; >>>> >>>> #5; >>>> clk = 1; >>>> >>>> >>>> end // initial begin >>>> >>>> initial >>>> begin >>>> $dumpfile ("counter.vcd"); >>>> $dumpvars; >>>> end >>>> >>>> initial >>>> begin >>>> $display("\t\ttime,\tclk,\tin,\tout,\treset,\tload"); $monitor("%d >>>> \t%d \t%d \t%b \t%b \t%b",$time, bin, bout, clk, reset, load); >>>> end >>>> >>>> endmodule // test >>>> >>>> >>>> >> >> >>Many thanks Arlet ! -- HBV
Reply by ●January 3, 20082008-01-03
Le Thu, 03 Jan 2008 15:31:26 +0100, Arlet Ottens a écrit:> Habib Bouaziz-Viallet wrote: > >> Le Thu, 03 Jan 2008 15:02:31 +0100, Arlet Ottens a écrit: >> >>> Habib Bouaziz-Viallet wrote: >>>> Hi all ! >>>> >>>> I simulate a simple design (synchronus RESET/LOAD 8-bits counter) with >>>> iverilog and testbench associated. Waveforms with gtkwave looks good. >>>> >>>> I have been trying to synthetise a simple 8bit counter within WebPack ISE >>>> 9.2 edition. >>>> >>>> The "Translate" phase failed : >>>> .... >>>> Writing NGD file "counter.ngd" ... >>>> Writing NGDBUILD log file "counter.bld"... >>>> NGDBUILD done. >>>> Process "Translate" failed >>>> >>>> ... >>>> >>>> What's wrong with this ? >>> Did it give you any specific errors ? (click on 'Errors' tab at the bottom). >>> >> No. But i have WARNING:Xst:2734 - Property "use_dsp48" is not applicable >> for this technology. (In Warnings TAB) >>> >>>> PS : >>>> /* ------------ SIMPLE 8 BITS Synchronous Counter -------------*/ >>>> `timescale 1ns / 1ps >>>> module counter(in, out, clk, reset, load); >>>> input [7:0] in; >>>> input clk; >>>> input reset; >>>> input load; >>>> output reg[7:0] out; >>>> >>>> /* Chargement synchrone par load */ >>>> always @(posedge clk) >>>> begin >>>> out<=out+1; >>>> if (reset==1) >>>> out[7:0] <= 0; >>>> else if(load==1) >>>> out[7:0] <= in[7:0]; >>>> end >>> You're doing two assignments to 'out' in the same clock cycle. >> That's right but i'm not sur that this is an issue in that case. I'm >> learning Verilog at the moment. Thanks. >>> Try: >>> >>> always @(posedge clk) >>> begin >>> if (reset==1) >>> out[7:0] <= 0; >>> else if(load==1) >>> out[7:0] <= in[7:0]; >>> else >>> out<=out+1; >>> end >>> > > I tried this counter module in ISE Webpack 9.2 in Linux, and it builds > fine. > > The test bench contains constructs that aren't synthesizable, such as > the delays, $display() calls, and the fact that it doesn't have any I/O > signals. > >>> >>> >>>> endmodule >>>> >>>> Here the test_bench associated >>>> >>>> >>>> module test(); >>>> >>>> reg [7:0] bin ; >>>> wire [7:0] bout ; >>>> reg clk, reset, load; // wire s, cout; >>>> >>>> counter counter_en_test(bin, bout, clk, reset, load); >>>> >>>> initial >>>> begin >>>> >>>> bin = 4'b00010111; >>>> clk = 0; >>>> load = 0; >>>> reset = 0; >>>> >>>> #5; >>>> clk = 1; >>>> load = 1; >>>> >>>> >>>> #5; >>>> clk = 0; >>>> load=0; >>>> >>>> #5; >>>> clk = 1; >>>> >>>> #5; >>>> clk = 0; >>>> >>>> #5; >>>> clk = 1; >>>> >>>> #5; >>>> clk = 0; >>>> load = 1; >>>> >>>> #5; >>>> clk = 1; >>>> >>>> #5; >>>> clk = 0; >>>> >>>> #5; >>>> clk = 1; >>>> >>>> >>>> end // initial begin >>>> >>>> initial >>>> begin >>>> $dumpfile ("counter.vcd"); >>>> $dumpvars; >>>> end >>>> >>>> initial >>>> begin >>>> $display("\t\ttime,\tclk,\tin,\tout,\treset,\tload"); $monitor("%d >>>> \t%d \t%d \t%b \t%b \t%b",$time, bin, bout, clk, reset, load); >>>> end >>>> >>>> endmodule // test >>>> >>>> >>>> >> >> >>The problem was that some files in ../bin/lin/ have not executing perms. i made this : chmod +x winds* or something ... and it compiles fine now ! Many thank ! -- HBV
Reply by ●January 3, 20082008-01-03
Habib Bouaziz-Viallet wrote:> Le Thu, 03 Jan 2008 15:31:26 +0100, Arlet Ottens a écrit: > >> Habib Bouaziz-Viallet wrote: >> >>> Le Thu, 03 Jan 2008 15:02:31 +0100, Arlet Ottens a écrit: >>> >>>> Habib Bouaziz-Viallet wrote: >>>>> Hi all ! >>>>> >>>>> I simulate a simple design (synchronus RESET/LOAD 8-bits counter) with >>>>> iverilog and testbench associated. Waveforms with gtkwave looks good. >>>>> >>>>> I have been trying to synthetise a simple 8bit counter within WebPack ISE >>>>> 9.2 edition. >>>>> >>>>> The "Translate" phase failed : >>>>> .... >>>>> Writing NGD file "counter.ngd" ... >>>>> Writing NGDBUILD log file "counter.bld"... >>>>> NGDBUILD done. >>>>> Process "Translate" failed >>>>> >>>>> ... >>>>> >>>>> What's wrong with this ? >>>> Did it give you any specific errors ? (click on 'Errors' tab at the bottom). >>>> >>> No. But i have WARNING:Xst:2734 - Property "use_dsp48" is not applicable >>> for this technology. (In Warnings TAB)yeah, I get those warnings all the time too.>>>>> PS : >>>>> /* ------------ SIMPLE 8 BITS Synchronous Counter -------------*/ >>>>> `timescale 1ns / 1ps >>>>> module counter(in, out, clk, reset, load); >>>>> input [7:0] in; >>>>> input clk; >>>>> input reset; >>>>> input load; >>>>> output reg[7:0] out; >>>>> >>>>> /* Chargement synchrone par load */ >>>>> always @(posedge clk) >>>>> begin >>>>> out<=out+1; >>>>> if (reset==1) >>>>> out[7:0] <= 0; >>>>> else if(load==1) >>>>> out[7:0] <= in[7:0]; >>>>> end>> I tried this counter module in ISE Webpack 9.2 in Linux, and it builds >> fine. > waouh ! Is it a GNU/Linux ditrib pb ? I'm running debian GNU/Linux.Ubuntu (Edgy), so it's debian based. I had to install the open motif libs, but that's it. What device are you targetting ?
Reply by ●January 3, 20082008-01-03
Le Thu, 03 Jan 2008 15:45:58 +0100, Arlet Ottens a écrit:> Habib Bouaziz-Viallet wrote: >> Le Thu, 03 Jan 2008 15:31:26 +0100, Arlet Ottens a écrit: >> >>> Habib Bouaziz-Viallet wrote: >>> >>>> Le Thu, 03 Jan 2008 15:02:31 +0100, Arlet Ottens a écrit: >>>> >>>>> Habib Bouaziz-Viallet wrote: >>>>>> Hi all ! >>>>>> >>>>>> I simulate a simple design (synchronus RESET/LOAD 8-bits counter) with >>>>>> iverilog and testbench associated. Waveforms with gtkwave looks good. >>>>>> >>>>>> I have been trying to synthetise a simple 8bit counter within WebPack ISE >>>>>> 9.2 edition. >>>>>> >>>>>> The "Translate" phase failed : >>>>>> .... >>>>>> Writing NGD file "counter.ngd" ... >>>>>> Writing NGDBUILD log file "counter.bld"... >>>>>> NGDBUILD done. >>>>>> Process "Translate" failed >>>>>> >>>>>> ... >>>>>> >>>>>> What's wrong with this ? >>>>> Did it give you any specific errors ? (click on 'Errors' tab at the bottom). >>>>> >>>> No. But i have WARNING:Xst:2734 - Property "use_dsp48" is not applicable >>>> for this technology. (In Warnings TAB) > > yeah, I get those warnings all the time too. > >>>>>> PS : >>>>>> /* ------------ SIMPLE 8 BITS Synchronous Counter -------------*/ >>>>>> `timescale 1ns / 1ps >>>>>> module counter(in, out, clk, reset, load); >>>>>> input [7:0] in; >>>>>> input clk; >>>>>> input reset; >>>>>> input load; >>>>>> output reg[7:0] out; >>>>>> >>>>>> /* Chargement synchrone par load */ >>>>>> always @(posedge clk) >>>>>> begin >>>>>> out<=out+1; >>>>>> if (reset==1) >>>>>> out[7:0] <= 0; >>>>>> else if(load==1) >>>>>> out[7:0] <= in[7:0]; >>>>>> end > >>> I tried this counter module in ISE Webpack 9.2 in Linux, and it builds >>> fine. >> waouh ! Is it a GNU/Linux ditrib pb ? I'm running debian GNU/Linux. > > Ubuntu (Edgy), so it's debian based. I had to install the open motif > libs, but that's it.Open motif ?? I have download this morning the huge file (1.7G) from Xilinx and just type ./setup as the promise and do weird thing as download ServicePack or something and ... finally it works (almost ... see my post)> > What device are you targetting ?Oh just CPLD's for the moment 'cause i'm trying to speak Verilog as well i speak C/C++. -- HBV
Reply by ●January 3, 20082008-01-03
Habib Bouaziz-Viallet <habib@rigel.systems> wrote: ...> >>>>>> I simulate a simple design (synchronus RESET/LOAD 8-bits counterPlease edit your quote to keep it readable -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply by ●January 4, 20082008-01-04
On 2008-01-03, Arlet Ottens <usenet+5@c-scape.nl> wrote:> Habib Bouaziz-Viallet wrote: >> always @(posedge clk) >> begin >> out<=out+1; >> if (reset==1) >> out[7:0] <= 0; >> else if(load==1) >> out[7:0] <= in[7:0]; >> end > > You're doing two assignments to 'out' in the same clock cycle.Doing more than one assignment to a signal is allowed for synthesizable code, both in Verilog and VHDL. The last assignment in the process block takes precedence. (This assumes that all assignments are done in the same process, if not you will have a whole bunch of problems...) It can allow for quite a bit more readable code in some cases, especially if you have a combinational block where you must be sure to always assign a value to a certain signal in order to avoid a latch. /Andreas
