Is it possible to define an Integer so it could be incremented and return to 0.

First of all, sorry for my English. What I want is:

variable int : integer range 0 to 64:=0;
begin
process
 begin
int := int + 1;
end process;


And the values:  0 1 2 3 4... 64 0 1 2 3 4 5....

But the real case is that :   0 1 2 3 4 ... 64 64 64 64 64 64 64

My best Regards

Pablo

On Fri, 11 Jan 2008 05:22:48 -0800 (PST), 
Pablo <pbantunez@gmail.com> wrote:

hi Pablo

>variable int : integer range 0 to 64:=0;
>begin
>process
> begin
>int := int + 1;
>end process;
>
>
>And the values:  0 1 2 3 4... 64 0 1 2 3 4 5....

You want wrap-around at some upper limit.

> But the real case is that :   0 1 2 3 4 ... 64 64 64 64 64 64 64

Really?  That seems strange.  You should get a runtime error when
you try to increment from 64 to 65, because 65 is outside the range of
the variable.

You can easily do it...

    if int < LIMIT then
      int := int + 1;
    else
      int := 0;
    end if;

However, if your limit is "all ones" in a binary number
(e.g. 31, 63, 127, 255) it may be simpler to use UNSIGNED
data instead of integer data.  UNSIGNED values are a
vector of std_logic bits, and arithmetic will wrap around
from (2**N)-1 to 0.

You may get more help on comp.lang.vhdl.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

> But the real case is that :   0 1 2 3 4 ... 64 64 64 64 64 64 64

You can easily do it...

    if int < LIMIT then
      int := int + 1;
    else
      int := 0;
    end if;


Shouldn't this be:

    if int < LIMIT then
      int := int + 1;
    else
      int := LIMIT ;
    end if;


BTW, I used something very similar to age items in a queue.

Regards,
G.

On Fri, 11 Jan 2008 09:20:48 -0800 (PST), ghelbig@lycos.com wrote:

>> But the real case is that :   0 1 2 3 4 ... 64 64 64 64 64 64 64
>
>You can easily do it...
>
>    if int < LIMIT then
>      int := int + 1;
>    else
>      int := 0;
>    end if;
>
>
>Shouldn't this be:
>
>    if int < LIMIT then
>      int := int + 1;
>    else
>      int := LIMIT ;
>    end if;

Quite possibly.  I understood the OP to mean that he wanted
wrap-to-zero behaviour, and was getting something different.
Either way makes sense, depending on the application.

Note that you can also get wrap-to-zero behaviour using "mod":

  int := (int + 1) mod (LIMIT+1);

but that is unlikely to be synthesisable unless LIMIT+1 is
an exact power of 2.

Apologies if I misled anyone.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

On Jan 11, 12:20 pm, ghel...@lycos.com wrote:
> > But the real case is that :   0 1 2 3 4 ... 64 64 64 64 64 64 64
>
> You can easily do it...
>
>     if int < LIMIT then
>       int := int + 1;
>     else
>       int := 0;
>     end if;
>
> Shouldn't this be:
>
>     if int < LIMIT then
>       int := int + 1;
>     else
>       int := LIMIT ;
>     end if;
>
> BTW, I used something very similar to age items in a queue.
>
> Regards,
> G.

G's code:
 if int < LIMIT then
   int := int + 1;
 else
   int := LIMIT ;
 end if;
-------

let's see..
initialize int to 0
LIMIT is 3
int < LIMIT ?  int
   Y            1
   Y            2
   Y            3
   N            3
   :            :
   N            3

-Dave Pollum

Thanks to everyone for your advices. It has been very usefull for me.

Pablo

On Jan 11, 8:09 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Fri, 11 Jan 2008 05:22:48 -0800 (PST),
>
> Pablo <pbantu...@gmail.com> wrote:
>
> hi Pablo
>
> >variable int : integer range 0 to 64:=0;
> >begin
> >process
> > begin
> >int := int + 1;
> >end process;
>
> >And the values:  0 1 2 3 4... 64 0 1 2 3 4 5....
>
> You want wrap-around at some upper limit.
>
> > But the real case is that :   0 1 2 3 4 ... 64 64 64 64 64 64 64
>
> Really?  That seems strange.  You should get a runtime error when
> you try to increment from 64 to 65, because 65 is outside the range of
> the variable.
>
> You can easily do it...
>
>     if int < LIMIT then
>       int := int + 1;
>     else
>       int := 0;
>     end if;
>
> However, if your limit is "all ones" in a binary number
> (e.g. 31, 63, 127, 255) it may be simpler to use UNSIGNED
> data instead of integer data.  UNSIGNED values are a
> vector of std_logic bits, and arithmetic will wrap around
> from (2**N)-1 to 0.
>
> You may get more help on comp.lang.vhdl.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.

If the limit were "all ones" (2**N-1, which it is not in this case),
then you could just:

int := (int + 1) mod LIMIT+1;

And it will synthesize without additional hardware.

If LIMIT+1 /= 2**N, the the above will still simulate correctly in a
test bench, but most synthesis tools will not accept it (rem, mod or
divide by non-integral power of two).

Again, this is a rollover, not a saturate behavior.

Andy

Finally I have tried to implement my desing with Mod Operator but all
the design seems to fail. This is my code:

if(read = '1' and fifo_empty='0') then
addr := (addr - 1)mod(2)
end if;

Now I have read in a news group that MOD operator is not synthesizable
when:

- A mod B when B is not a power of 2.
- A mod B when both A and B are not constant.

Exactly it says:
"a mod b" means "the remainder when a is divided by b. Note that
unless 'b' is a power of 2 or both a and b are constants, the mod
operation is most likely not synthesizable.


The first sentence is perfect, but the second one involves that the
operator has not sense.

Could someone tell me if this is true??

My best regards

Pablo

On Jan 22, 11:59=A0am, Pablo <pbantu...@gmail.com> wrote:
> Finally I have tried to implement my desing with Mod Operator but all
> the design seems to fail.

Are we supposed to guess what the failure is?

> This is my code:
>
> if(read =3D '1' and fifo_empty=3D'0') then
> addr :=3D (addr - 1)mod(2)
> end if;
>

So addr will count from 0 to 1 and back to 0....a toggle flip
flop....probably not what you want but that's what your posted code
will do.  I'll bet the simulator would catch that too, did you
simulate?

> Now I have read in a news group that MOD operator is not synthesizable
> when:
>
> - A mod B when B is not a power of 2.

Generally speaking that's true...that's why if you need a counter that
counts from 0 to 17 (or any other non power of 2 modulus) and back to
0, you code it so that if it equals 17 then reset it to 0....but I
digress.

> - A mod B when both A and B are not constant.
>
> Exactly it says:
> "a mod b" means "the remainder when a is divided by b. Note that
> unless 'b' is a power of 2 or both a and b are constants, the mod
> operation is most likely not synthesizable.
>
> The first sentence is perfect, but the second one involves that the
> operator has not sense.
>
Why does it not make sense? I'm assuming that you're confused about
the "or both a and b are constants" part of the second sentence
(again, take the time to let people know what exactly is your
confusion).  If A and B are both constants, then A mod B will also be
a constant and can be computed by the synthesis tool.  Here's another
hint, constants do not get synthesized....as logic in terms of
gates....they reduce down to things that are always either '1' or
'0'...which is used in the logic optomization process.

Kevin Jennings

On 22 ene, 18:18, KJ <kkjenni...@sbcglobal.net> wrote:
> On Jan 22, 11:59 am, Pablo <pbantu...@gmail.com> wrote:
>
> > Finally I have tried to implement my desing with Mod Operator but all
> > the design seems to fail.
>
> Are we supposed to guess what the failure is?
>
> > This is my code:
>
> > if(read = '1' and fifo_empty='0') then
> > addr := (addr - 1)mod(2)
> > end if;
>
> So addr will count from 0 to 1 and back to 0....a toggle flip
> flop....probably not what you want but that's what your posted code
> will do.  I'll bet the simulator would catch that too, did you
> simulate?
>
> > Now I have read in a news group that MOD operator is not synthesizable
> > when:
>
> > - A mod B when B is not a power of 2.
>
> Generally speaking that's true...that's why if you need a counter that
> counts from 0 to 17 (or any other non power of 2 modulus) and back to
> 0, you code it so that if it equals 17 then reset it to 0....but I
> digress.
>
> > - A mod B when both A and B are not constant.
>
> > Exactly it says:
> > "a mod b" means "the remainder when a is divided by b. Note that
> > unless 'b' is a power of 2 or both a and b are constants, the mod
> > operation is most likely not synthesizable.
>
> > The first sentence is perfect, but the second one involves that the
> > operator has not sense.
>
> Why does it not make sense? I'm assuming that you're confused about
> the "or both a and b are constants" part of the second sentence
> (again, take the time to let people know what exactly is your
> confusion).  If A and B are both constants, then A mod B will also be
> a constant and can be computed by the synthesis tool.  Here's another
> hint, constants do not get synthesized....as logic in terms of
> gates....they reduce down to things that are always either '1' or
> '0'...which is used in the logic optomization process.
>
> Kevin Jennings

Thanks kevin, I will try to explain as better as possible. Of course,
my English is not perfect.

My real code is this:

if(read='1' and empty='0') then
addr := (addr + 1)mod(64);                      -- So as you said,
addr INCREMENTS its value until 64. In this moment it init to 0.
That's the use of mod.
end if;

My confusion is the following:

Addr is defined as an Integer Variable in the proccess body. Of course
is not constant, so its value is increment in each clock cycle.
So: Could I use mod in my code???  Could Mod operator be used with
variables or signals??

Thanks so much