Debbuging a RISC processor on an FPGA

Hi

I have implemented a RISC architecure and RTL simulation in Modelsim 
works fine. So the next step would be to run this architecture on an
FPGA and see if it still outputs the correct results. So far my only 
idea is go use Chipscope to connect to the core and then try to read out
the register contents as soon as the computation of the program has 
finished. Until now I just used Chipscope to debug simple design where
I just had debugg one output value and not a set of registers.

Are their maybe other approaches that I could use to see if the 
sythesized core does the same as the simulated one?

Would be thankful for other ideas

Thanks!

"pg4100" <pg4100@yahoo.co.uk> wrote in message news:fmfqhm$a86$1@aioe.org...
> Hi
>
> I have implemented a RISC architecure and RTL simulation in Modelsim works 
> fine. So the next step would be to run this architecture on an
> FPGA and see if it still outputs the correct results. So far my only idea 
> is go use Chipscope to connect to the core and then try to read out
> the register contents as soon as the computation of the program has 
> finished. Until now I just used Chipscope to debug simple design where
> I just had debugg one output value and not a set of registers.
>
> Are their maybe other approaches that I could use to see if the sythesized 
> core does the same as the simulated one?

What about adding a simple UART or low-cost HD44780 (or compatible) LCD 
displays to your processor.

Hans
www.ht-lab.com


>
> Would be thankful for other ideas
>
> Thanks! 

> Are their maybe other approaches that I could use to see if the
> sythesized core does the same as the simulated one?


For a CPU that I designed once, I setup an automated testing platform
where I ...

- ran a small, simple test case on the CPU, and recorded changes in
the program counter (PC)
- fed the recorded PCs back into my desktop computer ... (for this
particular design, I was able to use an existing serial connection)
- I wrote a small C program to gather the results coming in the serial
port and analyze the PCs that were output by the CPU (to compare it to
expected results)

I had a suite of several test cases which tested various ADD, MULT,
etc. instructions, and these were often used to JMP to different
locations (thereby changing the PC).  Any differences in the program
counter were automatically picked up by the C software when it
analyzed the "trace" of PCs.

This took a bit of time to get working perfectly (i.e., you have to
design the test cases and the C program correctly :), but as a real
believer in automated testing, I feel that it saved me a fair bit of
time down the road.

K.

> - ran a small, simple test case on the CPU, and recorded changes in
> the program counter (PC)
> - fed the recorded PCs back into my desktop computer ... (for this
> particular design, I was able to use an existing serial connection)
> - I wrote a small C program to gather the results coming in the serial
> port and analyze the PCs that were output by the CPU (to compare it to
> expected results)

Interesting approach I have to admit. But is in my case probably not 
applicable as I execute programs that include almost no jmp or branch 
instructions. So for me it is essential that I could read out the 
register content or maybe the RAM content at the end of the computation.

Would be thankful for more such ideas ;)

> What about adding a simple UART or low-cost HD44780 (or compatible) LCD 
> displays to your processor.

Hm LCD Display would be interesting. The problem is, that I have zero 
experience with this kind of approach. So I dont know how difficult it 
would be to connect such a LCD display.. is it straightforward?

"pg4100" <pg4100@yahoo.co.uk> wrote in message news:fmg17p$1ur$1@aioe.org...
>> What about adding a simple UART or low-cost HD44780 (or compatible) LCD 
>> displays to your processor.
>
> Hm LCD Display would be interesting. The problem is, that I have zero 
> experience with this kind of approach. So I dont know how difficult it 
> would be to connect such a LCD display.. is it straightforward?

Have a look on the web, there are lots of projects that use the Hitachi 
HD44780 (or compatible) controller chip. The interface is a simple 4/8 bits 
bus with some strobe signals.

http://en.wikipedia.org/wiki/HD44780_Character_LCD

You can hook one up to your parallel port (assuming you still have one) and 
experiment with it first before you connect it to your processor.

http://www.beyondlogic.org/parlcd/parlcd.htm

You can find these modules on ebay for very little money.

Hans
www.ht-lab.com

Are you using one of the xilinx development boards?  IF so you could make 
use of the on-board LCD or if you have an older model board the 7
segment LED display.

"pg4100" <pg4100@yahoo.co.uk> wrote in message news:fmg17p$1ur$1@aioe.org...
>> What about adding a simple UART or low-cost HD44780 (or compatible) LCD 
>> displays to your processor.
>
> Hm LCD Display would be interesting. The problem is, that I have zero 
> experience with this kind of approach. So I dont know how difficult it 
> would be to connect such a LCD display.. is it straightforward?
> 

Hi,

Make sure that your test program both works in simulation and on target 
since you will need to go back and forth between them.

Create small assembler programs that test one feature (instruction) each and 
make them self-checking.
You could make your programs to light one of two led to show if that program 
succeeded or not.

This way you can run them in simulation and on a board.

Then it's just a large labour of writing all programs for all features that 
you want to test.

G�ran

"pg4100" <pg4100@yahoo.co.uk> wrote in message news:fmfqhm$a86$1@aioe.org...
> Hi
>
> I have implemented a RISC architecure and RTL simulation in Modelsim works 
> fine. So the next step would be to run this architecture on an
> FPGA and see if it still outputs the correct results. So far my only idea 
> is go use Chipscope to connect to the core and then try to read out
> the register contents as soon as the computation of the program has 
> finished. Until now I just used Chipscope to debug simple design where
> I just had debugg one output value and not a set of registers.
>
> Are their maybe other approaches that I could use to see if the sythesized 
> core does the same as the simulated one?
>
> Would be thankful for other ideas
>
> Thanks! 

Thanks for your feedback Goeran, the simlation in the Modelsim works 
fine. I have a PCI card, so the LEDS approach sounds good but I have 
already written some kind of libraray with different applications and I 
wanna see if they also work on the FPGA and not only in the simulation.

So I was thinking of having the program counter as my trigger, so when
the end is reached then I wanna somehow read out the values of the 
register with Chipscope. Or each time the program counter changes I read 
out the values of the Registers to see if the results are as expected 
and could so also immediately identify the instructions that have caused 
problems. SO far i have just debugged a simple counter with the 
chipscope so I hope the approach with the RISC also works as I have just 
described.




G�ran Bilski wrote:
> Hi,
> 
> Make sure that your test program both works in simulation and on target 
> since you will need to go back and forth between them.
> 
> Create small assembler programs that test one feature (instruction) each and 
> make them self-checking.
> You could make your programs to light one of two led to show if that program 
> succeeded or not.
> 
> This way you can run them in simulation and on a board.
> 
> Then it's just a large labour of writing all programs for all features that 
> you want to test.
> 
> G�ran
> 
> "pg4100" <pg4100@yahoo.co.uk> wrote in message news:fmfqhm$a86$1@aioe.org...
>> Hi
>>
>> I have implemented a RISC architecure and RTL simulation in Modelsim works 
>> fine. So the next step would be to run this architecture on an
>> FPGA and see if it still outputs the correct results. So far my only idea 
>> is go use Chipscope to connect to the core and then try to read out
>> the register contents as soon as the computation of the program has 
>> finished. Until now I just used Chipscope to debug simple design where
>> I just had debugg one output value and not a set of registers.
>>
>> Are their maybe other approaches that I could use to see if the sythesized 
>> core does the same as the simulated one?
>>
>> Would be thankful for other ideas
>>
>> Thanks! 
> 
> 

On Mon, 14 Jan 2008 14:11:02 +0000, pg4100 wrote:

> Hi
> 
> I have implemented a RISC architecure and RTL simulation in Modelsim
> works fine. So the next step would be to run this architecture on an
> FPGA and see if it still outputs the correct results. So far my only
> idea is go use Chipscope to connect to the core and then try to read out
> the register contents as soon as the computation of the program has
> finished. Until now I just used Chipscope to debug simple design where I
> just had debugg one output value and not a set of registers.
> 
> Are their maybe other approaches that I could use to see if the
> sythesized core does the same as the simulated one?
> 
> Would be thankful for other ideas
> 
> Thanks!

	One thing I have done is make a special debug version of the processor,
and bring out the interesting bits (pipelines,registers,PC, status) so
they are readable by the host (you mentioned you had a PCI card...). Then
I have a single clock register that clocks the CPU when written to. This
hardware is accessed by a simple disassembler/singlestep program running
on the host...