Programmable clock, FPGA PLLs, and Actel PLL Core

Escenario : Need a clock system with range from ~50Mhz to 150Mhz with
as much granularity as possible to drive an FPGA.


Could anyone please suggest options on how to better implement this
clock system.? I've looked at programmable clocks from Cypress,
Maxim-ic, but these require some I2C or 2-wire interface, and I don't
have a microcontroller on board, just the FPGA so I'd need to put a
I2C core...  . I've looked at using the PLL core in the FPGA (Actel in
this case), but I find the documentation about it to be extremely poor
as to how to really implement it.

By the way, if anybody has had experience using the PLL core in Actel,
could you please give a simple example on how to use the core
generated by "Actgen." I've read the document on "PLL dynamic
reconfiguration using JTAG," and I still don't understand
completely....

Thanks in advance,

David

Peter,

In article <402BBFA1.49FA2DB5@xilinx.com>
> You need to be more specific about granularity, jitter, and your budget.
> Here is one extreme:
> I am just finishing a project where we combine a small Spartan3 plus an
> ICS8735 PLL to generate 1 Hz to 640 MHz with a granularity of 1 Hz  (all
> the way to 640 MHz ! ) and very low jitter (hopefully below 50 ps). This
> uses some unconventional tricks...

Any plans to make an application note describing your setup? It sounds 
like a very cool design.

Are you doing something like frequency division in the FPGA with 
counters and multiplication with the PLL? Perhaps using different clocks 
& divider combos to cover the range??

Thanks,
Jay.

You need to be more specific about granularity, jitter, and your budget.
Here is one extreme:
I am just finishing a project where we combine a small Spartan3 plus an
ICS8735 PLL to generate 1 Hz to 640 MHz with a granularity of 1 Hz  (all
the way to 640 MHz ! ) and very low jitter (hopefully below 50 ps). This
uses some unconventional tricks...

DDS is the traditional method to achieve finest granularity, but it
creates lots of jitter, and is non-trivial at 150 MHz.

Peter Alfke
===================================
dave wrote:
> 
> Escenario : Need a clock system with range from ~50Mhz to 150Mhz with
> as much granularity as possible to drive an FPGA.
> 
> Could anyone please suggest options on how to better implement this
> clock system.? I've looked at programmable clocks from Cypress,
> Maxim-ic, but these require some I2C or 2-wire interface, and I don't
> have a microcontroller on board, just the FPGA so I'd need to put a
> I2C core...  . I've looked at using the PLL core in the FPGA (Actel in
> this case), but I find the documentation about it to be extremely poor
> as to how to really implement it.
> 
> By the way, if anybody has had experience using the PLL core in Actel,
> could you please give a simple example on how to use the core
> generated by "Actgen." I've read the document on "PLL dynamic
> reconfiguration using JTAG," and I still don't understand
> completely....
> 
> Thanks in advance,
> 
> David

Jay, give me a few weeks to publish.
In a nutshell:  10 MHz xtal osc gets multiplied to 80 MHz, drives Direct
Digital Synthesis accumulator, a "magic circuit" then multiplies the
frequency and reduces the jitter. The Spartan-3 output drives the ICS
PLL for further jitter reduction and multiplication by up to 8.
Nice GUI and display control by PicoBlaze.
Read about it in XCell, and I will also brag about characterization
results in this ng, once we are finished.  Fun project  :-)

Peter Alfke  
================================
Jay wrote:
> 
> Peter,
> 
> In article <402BBFA1.49FA2DB5@xilinx.com>
> > You need to be more specific about granularity, jitter, and your budget.
> > Here is one extreme:
> > I am just finishing a project where we combine a small Spartan3 plus an
> > ICS8735 PLL to generate 1 Hz to 640 MHz with a granularity of 1 Hz  (all
> > the way to 640 MHz ! ) and very low jitter (hopefully below 50 ps). This
> > uses some unconventional tricks...
> 
> Any plans to make an application note describing your setup? It sounds
> like a very cool design.
> 
> Are you doing something like frequency division in the FPGA with
> counters and multiplication with the PLL? Perhaps using different clocks
> & divider combos to cover the range??
> 
> Thanks,
> Jay.

Peter Alfke wrote:

> Jay, give me a few weeks to publish.
> In a nutshell:  10 MHz xtal osc gets multiplied to 80 MHz, drives Direct
> Digital Synthesis accumulator, a "magic circuit" then multiplies the
> frequency and reduces the jitter. The Spartan-3 output drives the ICS
> PLL for further jitter reduction and multiplication by up to 8.
> Nice GUI and display control by PicoBlaze.
> Read about it in XCell, and I will also brag about characterization
> results in this ng, once we are finished.  Fun project  :-)

  Yes, sounds a great 'dynamic range' demonstration.
I've changed the topic heading if you want to keep us posted :)

  Any plans to add a 640MHz reciprocal Frequency counter - or
do you have this included already, just to prove the Synth is
on the right frequency :)

-jg

Frequency counter is the next project. Since we have case, power supply,
display and all the mechanical trivia established, it is easy to build a
separate frequency counter, 1 Hz to 1.5 GHz with 9 digits of display.
Time base oscillator promises < 3 ppm (Maxim).
The "reciprocal" concept made it into a Xilinx "UltraController"
presentation and demo.
I will use the MultiGigabit Transceiver for the input. 3 Gbps = 1.5 MHz.
 I could use the newest Virtex-II ProX which is 3 times faster, but I do
not see so much demand for a 5 GHz input resolution (LVDS).  Gettinga
bit esoteric, but the chip can do it...
Keep you posted.

Peter Alfke
==========================
Jim Granville wrote:
> 
> 
>   Yes, sounds a great 'dynamic range' demonstration.
> I've changed the topic heading if you want to keep us posted :)
> 
>   Any plans to add a 640MHz reciprocal Frequency counter - or
> do you have this included already, just to prove the Synth is
> on the right frequency :)
> 
> -jg

Peter Alfke wrote:
> Frequency counter is the next project. Since we have case, power supply,
> display and all the mechanical trivia established, it is easy to build a
> separate frequency counter, 1 Hz to 1.5 GHz with 9 digits of display.
> Time base oscillator promises < 3 ppm (Maxim).
> The "reciprocal" concept made it into a Xilinx "UltraController"
> presentation and demo.
> I will use the MultiGigabit Transceiver for the input. 3 Gbps = 1.5 MHz.
>  I could use the newest Virtex-II ProX which is 3 times faster, but I do
> not see so much demand for a 5 GHz input resolution (LVDS).  Gettinga
> bit esoteric, but the chip can do it...
> Keep you posted.

Thanks,
  Will this fit into your 'small spartan 3', alongside the Synth ?
  Can you feed the 1.5GHz into a flip flop / ring counter reliably ?
  What about Fmax of a variable modulus divider 1st stage ?
  (was it the 11C90 (?) from fairchild ?)

-jg

Thank you for your reply Mr. Alfke. 

Your project does sound very interesting. I think that what I'm
looking for is way too much simpler than that. 1 Hz granularity would
be very nice, but I could work with 1Mhz steps ok. At this point I
really just need clocks ~60Mhz, ~100Mhz and 150Mhz, but having some -+
range arround these frequencies would help me a lot too.

Ideally I could use the PLL core on the FPGA to input a fixed
frequency clock (150Mhz) and have it output the frequencies I need
(~60, ~100, ~150 MHz) -- one at a time, not all three at the same
time, I would select which one through internal logic or JTAG. This
ouput clock is the one driving my whole FPGA logic inside.

I've been having a hard time understanding the usage of the PLL
component in ACTEL and the documentation is not really helping me
much. So, I'm open to suggestions, while I keep trying to even get the
PLL core to synthezise.

I'll keep an eye on Xilinx's magazine for your published project
because it does sound interesting.


Thanks again,

David.

11C90, 10/11 ECL variable modulus prescaler, memories of the early
'seventies...It's amazing that we could build frequency synthesizers
running close to a GHz at that time. Lots of power though, and tricky
pc-board layout. Now it's so much more integrated, and one can easily
recover from design mistakes. I love FPGAs !

The trouble with a fast front-end in our FPGAs is that almost everything
has gotten much faster ( and more sophisticated ) in the past 5 years,
but the raw toggle frequency of a LUT+flip-flop has not doubled from the
400 MHz we could do 5years ago in XC4000XL. The flip-flop is much
faster, but the routing, although flexible, is less direct. That's why I
have given up doing it that way.

The MGTs in Virtex-II Pro can receive 3.125 gigabits/sec, which means
1.5 GHz.
And there is an easy way to bypass lots of stuff, and represent 20
incoming bits in parallel. The rest is just design at 150 MHz. Not difficult.

Anybody need a counter with resolution between 1.5 and 5 GHz ?
Peter Alfke
=================================
Jim Granville wrote:
> 
> Peter Alfke wrote:
> > Frequency counter is the next project. Since we have case, power supply,
> > display and all the mechanical trivia established, it is easy to build a
> > separate frequency counter, 1 Hz to 1.5 GHz with 9 digits of display.
> > Time base oscillator promises < 3 ppm (Maxim).
> > The "reciprocal" concept made it into a Xilinx "UltraController"
> > presentation and demo.
> > I will use the MultiGigabit Transceiver for the input. 3 Gbps = 1.5 MHz.
> >  I could use the newest Virtex-II ProX which is 3 times faster, but I do
> > not see so much demand for a 5 GHz input resolution (LVDS).  Gettinga
> > bit esoteric, but the chip can do it...
> > Keep you posted.
> 
> Thanks,
>   Will this fit into your 'small spartan 3', alongside the Synth ?
>   Can you feed the 1.5GHz into a flip flop / ring counter reliably ?
>   What about Fmax of a variable modulus divider 1st stage ?
>   (was it the 11C90 (?) from fairchild ?)
> 
> -jg

Let me put in a plug for the Digital Clock Manager in Virtex-II.
It can take in any frequency between 1MHz and >300 MHz, and
simultaneously multiply and divide it by two numbers in the range of
1...32. (Output frequency must be >24 MHz, though).
You can do 200 MHz times 15, divided by 19 if you feel like it. The fact
that 200 MHz times 15 is very high does not matter, the DCM does the
mathematical manipulation without going to GHz...
So you can generate your frequencies from many different input sources,
but only one frequency per DCM. You can reprogram the DCM on the fly,
but it is somewhat complicated in today's circuits.
Peter Alfke
=================
dave wrote:
> 
> Thank you for your reply Mr. Alfke.
> 
> Your project does sound very interesting. I think that what I'm
> looking for is way too much simpler than that. 1 Hz granularity would
> be very nice, but I could work with 1Mhz steps ok. At this point I
> really just need clocks ~60Mhz, ~100Mhz and 150Mhz, but having some -+
> range arround these frequencies would help me a lot too.
> 
> Ideally I could use the PLL core on the FPGA to input a fixed
> frequency clock (150Mhz) and have it output the frequencies I need
> (~60, ~100, ~150 MHz) -- one at a time, not all three at the same
> time, I would select which one through internal logic or JTAG. This
> ouput clock is the one driving my whole FPGA logic inside.
> 
> I've been having a hard time understanding the usage of the PLL
> component in ACTEL and the documentation is not really helping me
> much. So, I'm open to suggestions, while I keep trying to even get the
> PLL core to synthezise.
> 
> I'll keep an eye on Xilinx's magazine for your published project
> because it does sound interesting.
> 
> Thanks again,
> 
> David.