Basic FPGA question about Reset

Hi

I have a very basic question. I have a design that has a clk and reset 
input. I know that I have to connect the clk and the reset inputs to
the corresponding pins of the FPGA. But how can i now assert a reset 
signal for 8ns to my design to initialise some values? I dont think that 
I have a reset button ;). can I specify this maybe somehow in the UCF file?

thanks for help!
Jey

"jey" <jey_1453@hotmail.com> wrote in message news:fml0qo$qnd$1@aioe.org...
> Hi
>
> I have a very basic question. I have a design that has a clk and reset 
> input. I know that I have to connect the clk and the reset inputs to
> the corresponding pins of the FPGA. But how can i now assert a reset 
> signal for 8ns to my design to initialise some values? I dont think that I 
> have a reset button ;). can I specify this maybe somehow in the UCF file?
>
> thanks for help!
> Jey

Hi Jey,

No, you can't set this in the UCF. However, in most FPGAs, the state of the 
design is set to a known state on configuration, usually in the source code. 
At other times, you must have an input somewhere to initiate reset, correct?

Also, I suggest this link.

http://www.xilinx.com/support/documentation/white_papers/wp272.pdf

HTH., Syms.

p.s. It looks like the Xilinx techxclusives have been resurrected as white 
papers.

"jey" <jey_1453@hotmail.com> wrote in message news:fml3mi$3p0$1@aioe.org...
>> No, you can't set this in the UCF. However, in most FPGAs, the state of 
>> the design is set to a known state on configuration, usually in the 
>> source code. At other times, you must have an input somewhere to initiate 
>> reset, correct?
>>
>
> Thanks for your comments Symon. I have a design where a reset signal is 
> required for lets say some clock cycles to initialise the status of my 
> design. So I wonder how this can be done easy? Having an own reset module 
> is probably also a little bit akward, isnt it?
>
> cheers!

Hi Jey,
Does this reset only happen once? I.e. at configuration time?
Cheers, Syms. 

> No, you can't set this in the UCF. However, in most FPGAs, the state of the 
> design is set to a known state on configuration, usually in the source code. 
> At other times, you must have an input somewhere to initiate reset, correct?
> 

Thanks for your comments Symon. I have a design where a reset signal is 
required for lets say some clock cycles to initialise the status of my 
design. So I wonder how this can be done easy? Having an own reset 
module is probably also a little bit akward, isnt it?

cheers!

On Jan 16, 9:17 am, jey <jey_1...@hotmail.com> wrote:
> > No, you can't set this in the UCF. However, in most FPGAs, the state of the
> > design is set to a known state on configuration, usually in the source code.
> > At other times, you must have an input somewhere to initiate reset, correct?
>
> Thanks for your comments Symon. I have a design where a reset signal is
> required for lets say some clock cycles to initialise the status of my
> design. So I wonder how this can be done easy? Having an own reset
> module is probably also a little bit akward, isnt it?
>
> cheers!

Jey;

You could use a separate chip to reset the FPGA, such as a one-shot or
a voltage supervisor that has a reset push button input.
HTH
-Dave Pollum

> You could use a separate chip to reset the FPGA, such as a one-shot or
> a voltage supervisor that has a reset push button input.
> HTH

Thanks Dave, was some sort of hoping that there is any simpler way as 
that I could do it without an additonal hardware source. It there a way 
to do that with Chipscope? Maybe with a VIO core?

Cheers,

Yes!

The tech-X's were scrubbed, and polished, and the more useful ones will
re-appear in the coming months as white papers.

If someone REALLY wants an old tech-X, email me, as we have retrieved
the tape, and placed the old web pages on an internal server as a means
of supporting folks.... (I know, it isn't like this shouldn't have been
done in the first place, well, let us just say 'a lesson learned."

Austin

Symon wrote:
> "jey" <jey_1453@hotmail.com> wrote in message news:fml0qo$qnd$1@aioe.org...
>> Hi
>>
>> I have a very basic question. I have a design that has a clk and reset 
>> input. I know that I have to connect the clk and the reset inputs to
>> the corresponding pins of the FPGA. But how can i now assert a reset 
>> signal for 8ns to my design to initialise some values? I dont think that I 
>> have a reset button ;). can I specify this maybe somehow in the UCF file?
>>
>> thanks for help!
>> Jey
> 
> Hi Jey,
> 
> No, you can't set this in the UCF. However, in most FPGAs, the state of the 
> design is set to a known state on configuration, usually in the source code. 
> At other times, you must have an input somewhere to initiate reset, correct?
> 
> Also, I suggest this link.
> 
> http://www.xilinx.com/support/documentation/white_papers/wp272.pdf
> 
> HTH., Syms.
> 
> p.s. It looks like the Xilinx techxclusives have been resurrected as white 
> papers.
> 
> 

On Jan 16, 10:04=A0am, jey <jey_1...@hotmail.com> wrote:
> > You could use a separate chip to reset the FPGA, such as a one-shot or
> > a voltage supervisor that has a reset push button input.
> > HTH
>
> Thanks Dave, was some sort of hoping that there is any simpler way as
> that I could do it without an additonal hardware source. It there a way
> to do that with Chipscope? Maybe with a VIO core?
>
> Cheers,

Why not use a counter? The counter gets set to 0 at configuration, and
counts up after that until it gets to whatever value you choose. The
reset signal can be keyed from the count value. I usually like using
an on-board power-on-reset chip, but if you can't do that, this is
another way.

jey wrote:
> 
> Thanks for your comments Symon. I have a design where a reset signal is 
> required for lets say some clock cycles to initialise the status of my 
> design. So I wonder how this can be done easy? Having an own reset 
> module is probably also a little bit akward, isnt it?
> 
> cheers!

signal reset_shifter: std_logic_vector(5 downto 0) := "00000";
signal synchronous_reset: std_logic;

...

process(clk)
begin
   if rising_edge(clk) then
     reset_shifter <= reset_shifter(4 downto 0) & '1';
   end if;
end process;

synchronous_reset <= not reset_shifter(4);

-- Better yet, replace the '1' above with the "locked" output signal of 
the DLL that's generating the clock.

-Jeff

On Jan 16, 7:04 am, jey <jey_1...@hotmail.com> wrote:
> > You could use a separate chip to reset the FPGA, such as a one-shot or
> > a voltage supervisor that has a reset push button input.
> > HTH
>
> Thanks Dave, was some sort of hoping that there is any simpler way as
> that I could do it without an additonal hardware source. It there a way
> to do that with Chipscope? Maybe with a VIO core?
>
> Cheers,

I have seen a number of designs where unpredictable operation
(particularly FPGA's not loading reliably) was traced to a sloppy
reset circuit.

You should use a reset circuit external to the FPGA.  There are many
makers of suitable devices, they are often listed as 'microprocessor
supervisors'.

They are typically in the half-dollar price range, and make it easy to
generate a proper reset.

G.