Basic FPGA question about Reset

As other people have pointed out, you can specify the initial-state
of any flop, using a VHDL-attribute, or a Verilog 'initial' statement.

Verilog-2001 version:

wire my_one_shot_reset;   // active-high reset (fires once at 
FPGA-config/powerup!)
reg  [15:0] my_one_shot_ctr = 0;

always @ ( posedge clk ) begin : always_my_one_shot_ctr
  if ( my_one_shot_ctr < 10000 )
   my_one_shot_ctr <= my_one_shot_ctr + 1;
end // : always_my_one_shot_ctr

assign my_one_shot_reset = (my_one_shot_ctr < 10000);


"jey" <jey_1453@hotmail.com> wrote in message news:fml0qo$qnd$1@aioe.org...
> Hi
>
> I have a very basic question. I have a design that has a clk and reset 
> input. I know that I have to connect the clk and the reset inputs to
> the corresponding pins of the FPGA. But how can i now assert a reset 
> signal for 8ns to my design to initialise some values? I dont think that I 
> have a reset button ;). can I specify this maybe somehow in the UCF file?
>
> thanks for help!
> Jey 

>I mention this, because when I would force the FPGA to do my bidding,
>the product then failed the power on tests that AT&T had specified.  I
>passed when I let the FPGA do what it was designed to do.

What did the power look like for the case that failed?

I'd expect an external power-watcher chip would
get OR-ed in with the internal logic so you would
have the best of both worlds.  What went wrong?


Actually, now that I look more carefully, things get
complicated.

Is figure 23 in the Spartan3 data sheet the whole picture?

Are there restart paths not shown to handle power-not-good
(as detected by internal logic) while configuring?

What if PROG goes active during configuration?

What happens if INIT goes low after configuration has started?
It gets forced low by a bad CRC.  It would be handy if that
restarted the whole thing if you are configuring several devices
on a chain. 

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