Hi I have an VHDL core that is sythesizeable with the following tools Synopsys Design Compiler Cadence Encounter RTL Compiler Until now I was using XST for sythesis and it seems when I try to run sythesis for the VHDL core with XST I get a bunch of errors. The convenient thing with Xilinx was the Chipscope which allows the on-chip debugging. So I wonder if the tools mentioned at the beginning also support this kind of on-ship debugging? Or could I sythesise the design with the ICON and ILA with the Synopsis or Cadence RTL compiler and then use CHIPscope. Does anyone have tried that? Many thanks Philipp
Chipscope compatible with Synopsis or Cadence sythesise tools?
Started by ●January 17, 2008
Reply by ●January 17, 20082008-01-17
On 17 Jan, 18:39, Philipp <Philip...@hotmail.com> wrote:> Hi > > I have an VHDL core that is sythesizeable with the following tools > > =A0 =A0Synopsys Design Compiler > =A0 =A0Cadence Encounter RTL Compiler > > Until now I was using XST for sythesis and it seems when I try to run > sythesis for the VHDL core with XST I get a bunch of errors. The > convenient thing with Xilinx was the Chipscope which allows the on-chip > debugging. So I wonder if the tools mentioned at the beginning also > support this kind of on-ship debugging? Or could I sythesise the design > with the ICON and ILA with the Synopsis or Cadence RTL compiler and then > use CHIPscope. Does anyone have tried that?Do you have Xilinx .libs for DC or RC? Cheers, Jon
Reply by ●January 17, 20082008-01-17
On Jan 17, 1:39 pm, Philipp <Philip...@hotmail.com> wrote:> Hi > > I have an VHDL core that is sythesizeable with the following tools > > Synopsys Design Compiler > Cadence Encounter RTL Compiler > > Until now I was using XST for sythesis and it seems when I try to run > sythesis for the VHDL core with XST I get a bunch of errors. The > convenient thing with Xilinx was the Chipscope which allows the on-chip > debugging. So I wonder if the tools mentioned at the beginning also > support this kind of on-ship debugging? Or could I sythesise the design > with the ICON and ILA with the Synopsis or Cadence RTL compiler and then > use CHIPscope. Does anyone have tried that? > > Many thanks > PhilippThere is nothing to synthesize for chipscope icon and ila cores. You instantiate them as black boxes and the netlists for the cores will get pulled in during ngdbuild. Cheers, Jim http://home.comcast.net/~jimwu88/tools
Reply by ●January 17, 20082008-01-17
> There is nothing to synthesize for chipscope icon and ila cores. You > instantiate them as black boxes and the netlists for the cores will > get pulled in during ngdbuild.Makes sense, could give that a go! Hope it will work ;)
Reply by ●January 17, 20082008-01-17
> Do you have Xilinx .libs for DC or RC?No, at the moment I am just using the Xilinx stuff. Depends from whom (Xilinx or DC/RC) I could get this libs? hope they are for free. For what exactly do I need them?
Reply by ●January 17, 20082008-01-17
Philipp wrote:> Hi > > I have an VHDL core that is sythesizeable with the following tools > > Synopsys Design Compiler > Cadence Encounter RTL Compiler > > Until now I was using XST for sythesis and it seems when I try to run > sythesis for the VHDL core with XST I get a bunch of errors. The > convenient thing with Xilinx was the Chipscope which allows the on-chip > debugging. So I wonder if the tools mentioned at the beginning also > support this kind of on-ship debugging? Or could I sythesise the design > with the ICON and ILA with the Synopsis or Cadence RTL compiler and then > use CHIPscope. Does anyone have tried that?I'll admit that if you are doing debugging, then instantiating the cores in your HDL design seems to be the hard way (but maybe that is just me). Have you tried the core inserter instead? It inserts the ILA post synthesis, so it doesn't matter what synthesis tool you use. If you have tried the inserter, what is it that you prefer about instantiating into the HDL code. I find using the core inserter a quick and flexible process.
Reply by ●January 17, 20082008-01-17
> I'll admit that if you are doing debugging, then instantiating the cores > in your HDL design seems to be the hard way (but maybe that is just me). > Have you tried the core inserter instead? It inserts the ILA post > synthesis, so it doesn't matter what synthesis tool you use. > > If you have tried the inserter, what is it that you prefer about > instantiating into the HDL code. I find using the core inserter a quick > and flexible process.Yes I tried using it but it didnt work :D. With the core inserter I never got any data back from the device whereas with the direct instantiation in the code it was working. Rather strange...probably I should give it a go again, i think i have done something wrong with the clock connection!
Reply by ●January 17, 20082008-01-17
On 2008-01-17, Philipp <Philipp_G@hotmail.com> wrote:> > Yes I tried using it but it didnt work :D. With the core inserter I > never got any data back from the device whereas with the direct > instantiation in the code it was working.When using the inserter you may need to set preserve or keep attributes on the signals you want to instrument. Otherwise the optimizations done by your tools may cause problems. The most obvious would be one that is optimized out of the design, but there are more subtle pitfalls. Also don't forget to set 'trigger same as data' or hook up a real trigger. The first time I set one up in EDK I didn't realize the checkbox for that was off-screen (reachable only with a scrollbar) and didn't understand why I could never trigger... -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/
Reply by ●January 17, 20082008-01-17
The Xilinx .libs for DC or RC....is the list of lowlevel Xilinx gates. When you synthesize you map the rtl to a set of "low" level gates specified by a library. Say you had RTL code wire [31:0] a,b,c; assign {carry,c}=a+b; If the library had a 32bit adder as a low level cell. It would map 1 cell. If the library has 4bits adders as the primitive it maps 4 of those. The xilinx library would tell the synthesizer which primitives to map to. Xilinx would normally provide the library. The price is variable. some companies will give it away to potential bulk chip buyers. But since Xilinx has a synthesizer and contracts with Mentor, they are liekly to charge for it. "Philipp" <Philipp_G@hotmail.com> wrote in message news:fmo878$fnl$2@aioe.org...>> Do you have Xilinx .libs for DC or RC? > > No, at the moment I am just using the Xilinx stuff. Depends > from whom (Xilinx or DC/RC) I could get this libs? hope they are for free. > For what exactly do I need them?
Reply by ●January 17, 20082008-01-17
Dwayne Dilbeck wrote:> > Xilinx would normally provide the library. The price is variable. some > companies will give it away to potential bulk chip buyers. But since Xilinx > has a synthesizer and contracts with Mentor, they are liekly to charge for > it.Xilinx has never charged for synthesis or simulation libraries. It's been a long time since I've seen any requests for Synopsys synthesis so I had to go check to see if we were still shipping these with each release. I can see that they are still in the 9.2i release tree under $XILINX/synopsys but the files might only be included with the Solaris and Linux installers. If you don't have them contact your FAE or the hotline and they should be able to get you a copy. BTW, I wouldn't expect to see these around much longer. There must not have been any demand to add Synopsys DC support for Virtex-5 so that is definitely missing. Ed McGettigan -- Xilinx Inc.
