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How FPGA downconvert Giga SPS ADC data?

Started by fl January 20, 2008
Hi,
I have a question about ADC input to FPGA. Although I read some past
thread on ADC connection with ADC. I still don't understand how to
downconvert Giga Hz adc in FPGA. The new ADC, for example  ADC08D1500,
can support 1.5GSPS or even more. Its manufacture gives the demo
prototype which has Xilinx FPGA. To downconverter the ADC data, I
think the FPGA digital filter must be upto 1.5GSPS. Then, low throught
data can be obtained by decimation. The fastest multiplier in FPGA is
DSP48(?). It can be as fast as GSPS now? Could you tell me what's the
technique to downconvert GSPS data in FPGA? Thanks in advance.
On 20 jan, 15:15, fl <rxjw...@gmail.com> wrote:
> Hi, > I have a question about ADC input to FPGA. Although I read some past > thread on ADC connection with ADC. I still don't understand how to > downconvert Giga Hz adc in FPGA. The new ADC, for example =A0ADC08D1500, > can support 1.5GSPS or even more. Its manufacture gives the demo > prototype which has Xilinx FPGA. To downconverter the ADC data, I > think the FPGA digital filter must be upto 1.5GSPS. Then, low throught > data can be obtained by decimation. The fastest multiplier in FPGA is > DSP48(?). It can be as fast as GSPS now? Could you tell me what's the > technique to downconvert GSPS data in FPGA? Thanks in advance.
There should be several polyphase filters to do the filtering at the maximum FPGA speed, then decimation? It is still a little believable to me because I suspect the multiple polyphase filters need a lot of DSP48 to give an decent filter performance. What's your idea? Thanks.
Wide parallel data paths,

For example, suppose the conversion is one 12 bit sample every 1 ns: 
BUT the converter transfers 60 bits, every 5ns (one 60 bit word every 5 
ns, or a 200 MHz 60 bit wide data path.

Or, alternatively, the LVDS inputs are clocked on the rising, and 
falling edge of a 500 MHz clock, capturing 12 bits every 1 ns.

Then, inside the FPGA, the path is widened to 60 bits, and processing is 
done of 5 samples, at one time, every 5 ns.

So, no magic:  just acknowledge that the sample rate does not need to be 
equal to the system clock.

Austin
On Jan 20, 4:27=A0pm, austin <aus...@xilinx.com> wrote:
> Wide parallel data paths, > > For example, suppose the conversion is one 12 bit sample every 1 ns: > BUT the converter transfers 60 bits, every 5ns (one 60 bit word every 5 > ns, or a 200 MHz 60 bit wide data path. > > Or, alternatively, the LVDS inputs are clocked on the rising, and > falling edge of a 500 MHz clock, capturing 12 bits every 1 ns. > > Then, inside the FPGA, the path is widened to 60 bits, and processing is > done of 5 samples, at one time, every 5 ns. > > So, no magic: =A0just acknowledge that the sample rate does not need to be=
> equal to the system clock. > > Austin
Thank you very much. Yes. The wide bandwidth data coming into FPGA is the important first step. How about the downconversion? I feel the downconversion DDC part is still very difficult. I suppose that it should be here. For a wide band multichannel signal, how to demodulate them after IF or RF sampling?
Once sampled, it is "just data":  and as such, there are algorithms that 
do what you want.

I suggest you start by researching "sampled data systems" and read an 
introduction to digital signal processing.

You are asking very basic questions:  you may be a genius is some field, 
but you are a beginner in DSP, so you need to start at the beginning.

Austin
On 20 jan, 18:51, austin <aus...@xilinx.com> wrote:
> Once sampled, it is "just data": =A0and as such, there are algorithms that=
> do what you want. > > I suggest you start by researching "sampled data systems" and read an > introduction to digital signal processing. > > You are asking very basic questions: =A0you may be a genius is some field,=
> but you are a beginner in DSP, so you need to start at the beginning. > > Austin
Thank you very much. I am not genius at either side. I read and know a little about CORDIC in DDC at normal frequency (up to 100MHz in FPGA I think). I have the impression CORIDIC is relatively slow, because of iteration operation. In the mix of DDC, what maximum frequency can CORDIC achieve? I want to know the feasibility. Sure, I am reading a lot of DSP now. I am interested at : are there some difference in the architecture for high speed ADC data above GSPS? Thanks again.
fl wrote:
> On 20 jan, 18:51, austin <aus...@xilinx.com> wrote: >> Once sampled, it is "just data": and as such, there are algorithms that >> do what you want. >> >> I suggest you start by researching "sampled data systems" and read an >> introduction to digital signal processing. >> >> You are asking very basic questions: you may be a genius is some field, >> but you are a beginner in DSP, so you need to start at the beginning. >> >> Austin > > Thank you very much. I am not genius at either side. I read and know a > little about CORDIC in DDC at normal frequency (up to 100MHz in FPGA I > think). I have the impression CORIDIC is relatively slow, because of > iteration operation. In the mix of DDC, what maximum frequency can > CORDIC achieve? I want to know the feasibility. Sure, I am reading a > lot of DSP now. I am interested at : are there some difference in the > architecture for high speed ADC data above GSPS? Thanks again.
Iteration is only needed when extracting phase information from an input pair. Digital Down Conversion just modulates the ADC outputs by a fixed frequency. Modulating the inputs by a fixed phase for a single timestep is fully pipelined without iteration. The modulation is typically followed by halfband filter and Cascade Integrate Comb (CIC) stages. The halfband filters for the highest frequency doesn't have to be a lot of taps - it's a very small FIR filter. Fun stuff. Enjoy your reading! And visit andraka.com for some interesting information. - John_H