Hi, i am currently trying to figure out the number and values of a decoupling network for a spartan3e 500k (powered by the triple power supply from texas instruments TPS75003) .. i dont have the luxury of a software tool to help me simulate and analyse, but i just want a good estimate which can be supported by theoretic statements. I have read xapp623 (Power Distribution System (PDS) Design), and calculated the number and values of capacitors using the method in the application node. This is the results: Vccint - 1.2V 8 supply pins 1 - 4,7uF 2 - 0.47uF 5 - 0.047uF Vccaux - 2.5V 8 supply pins 1 - 4,7uF 2 - 0.47uF 5 - 0.047uF Vcco - 3.3V 14 supply pins 1 - 10uF 2 - 4.7uF 4 - 0.47uF 8 - 0.047uF So here i start wondering ... the application node method is to have one capacitor per vcc/gnd pin ... according to my knowledge (probably bad), the decoupling capacitors should be determined from the (frequency dependent)dynamic current requirement of the fpga. Since im designing the decoupling network for a unknown fpga utialization i am only interrested in the worst case scenario. If we take Vccint for example: 1.2V 5% tolerance - 2A max - 0.5ns risetimes Inorder for the voltage ripple to be under 5% for the bandwidth of 0.35/0.5ns = 700Mhz, the impedance of the PDS must be below : (1.2V*0.05)/2A = 0.03R Inorder for this to be realised i need INSANLY many decoupling capacitors. By placing 14 0.0047uF, 10 0.047uF, 2 0.47uF I can stay below 0.03R for a 80Mhz bandwith .... that means i still need to cover up to 700Mhz :/ .. but this result is far from what result i got from the xilinx application note .. I know that the previous calculations assumed that the current demand for the harmonics were 2A for the entire bandwidth, but how does the current relate to the harmonics of a signal transitions? if i got 50Mhz swiching frequency will the current drop with 20db/decade, just as the amplitude of the harmonics? regards kim
FPGA decoupling calculation
Started by ●January 22, 2008
Reply by ●January 22, 20082008-01-22
Hi Kim, I've not got much time so here's a few pointers:- IMO, Xilinx publish excessive requirements which covers their arse if anything should go wrong. Fair enough. However, you should know that it's fairly difficult to get this wrong, indeed, some folks (not me!) on this newsgroup apparently use very few bypass caps. Free capacitor parameter stuff.:- http://www.murata.com/designlib/mcsil/index.html Above a few 10's of MHz, all same sized caps have the same impedance. (See murata thing above) Just use 0402 1uF for everything. One per pin is more than enough. Make sure your board has a ground plane, try to use two vias for each cap terminal. Here's some stuff on where to place your caps. http://www.sigcon.com/pubsIndex.htm#bypass%20capacitors Or, ignore that stuff, sooo 20th C. Better bypass here:- http://www.x2y.com/ Finally, there are caps hidden in the FPGAs themselves. Go to your university's chemistry dept. and ask for some HF to find them! Also, STFW ! ;-) HTH, Syms.
Reply by ●January 22, 20082008-01-22
Symon <symon_brewer@hotmail.com> wrote:> Hi Kim, > I've not got much time so here's a few pointers:-> IMO, Xilinx publish excessive requirements which covers their arse if > anything should go wrong. Fair enough. However, you should know that it's > fairly difficult to get this wrong, indeed, some folks (not me!) on this > newsgroup apparently use very few bypass caps.If you route the Xilinx recommended number of CAPs, you either have no room for signal breakout or the bypass caps end up far away from the FPGA. The calculation also seems to forget about the interinsic C and L of the supply layers. My rule is: - try to implement a good ground plain, no swiss cheese - try to place one 0603/0402 cap in X5/7R near each supply pin with the traces to the FPGA as short as possible -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply by ●January 22, 20082008-01-22
"Uwe Bonnes" <bon@hertz.ikp.physik.tu-darmstadt.de> wrote in message news:fn4int$d1c$1@lnx107.hrz.tu-darmstadt.de...> Symon <symon_brewer@hotmail.com> wrote: >> Hi Kim, >> I've not got much time so here's a few pointers:- > >> IMO, Xilinx publish excessive requirements which covers their arse if >> anything should go wrong. Fair enough. However, you should know that it's >> fairly difficult to get this wrong, indeed, some folks (not me!) on this >> newsgroup apparently use very few bypass caps. > > If you route the Xilinx recommended number of CAPs, you either have no > room > for signal breakout or the bypass caps end up far away from the FPGA. The > calculation also seems to forget about the interinsic C and L of the > supply > layers. >Hi Uwe, Indeed. I notice their own dev. boards don't follow the XAPP recomendation. Hmmm. Cheers, Syms.
Reply by ●January 22, 20082008-01-22
On Tue, 22 Jan 2008 01:00:49 -0800 (PST), kislo <kislo02@student.sdu.dk> wrote:>... decoupling network ... > .. i dont have the luxury of a software tool to help me simulate and analyseThe headers in your post suggest you are using Windows. That's good, because you can download LTSpice and use that. http://www.linear.com/designtools/software/switchercad.jsp Like all simulations, the results are only as good as your models. In particular, you'll end up with lumped approximations which may result in resonances that don't appear on the real board. (The real board will have distributed capacitance, and also dielectric loss (which gets rid of a lot of the impedance peaks).) Regards, Allan
Reply by ●January 22, 20082008-01-22
On 22 Jan., 12:20, "Symon" <symon_bre...@hotmail.com> wrote:> "Uwe Bonnes" <b...@hertz.ikp.physik.tu-darmstadt.de> wrote in message > > news:fn4int$d1c$1@lnx107.hrz.tu-darmstadt.de... > > > > > Symon <symon_bre...@hotmail.com> wrote: > >> Hi Kim, > >> I've not got much time so here's a few pointers:- > > >> IMO, Xilinx publish excessive requirements which covers their arse if > >> anything should go wrong. Fair enough. However, you should know that it='s> >> fairly difficult to get this wrong, indeed, some folks (not me!) on thi=s> >> newsgroup apparently use very few bypass caps. > > > If you route the Xilinx recommended number of CAPs, you either have no > > room > > for signal breakout or the bypass caps end up far away from the FPGA. Th=e> > calculation also seems to forget about the interinsic C and L of the > > supply > > layers. > > Hi Uwe, > Indeed. I notice their own dev. boards don't follow the XAPP recomendation=.> Hmmm. > Cheers, Syms.- Skjul tekst i anf=F8rselstegn - > > - Vis tekst i anf=F8rselstegn -yea i noticed that too, the Spartan3E starter board dosent follow the XAPP recommendation
Reply by ●January 22, 20082008-01-22
On Jan 22, 4:00=A0am, kislo <kisl...@student.sdu.dk> wrote:>i dont have the luxury of a > software tool to help me simulate and analyse, but i just want a good > estimate which can be supported by theoretic statements.A spreadsheet can give a rough estimate as well...more later>I have read > xapp623 (Power Distribution System (PDS) Design), and calculated the > number and values of capacitors using the method in the application > node. This is the results: > Vccint - 1.2V 8 supply pins > =A0 1 - 4,7uF > =A0 2 - 0.47uF > =A0 5 - 0.047uF > > Vccaux - 2.5V 8 supply pins > =A0 1 - 4,7uF > =A0 2 - 0.47uF > =A0 5 - 0.047uF > > Vcco - 3.3V 14 supply pins > =A01 - 10uF > =A02 - 4.7uF > =A04 - 0.47uF > =A08 - 0.047uF > > So here i start wondering ... the application node method is to have > one capacitor per vcc/gnd pin ... according to my knowledge (probably > bad), the decoupling capacitors should be determined from the > (frequency dependent)dynamic current requirement of the fpga. Since im > designing the decoupling network for a unknown fpga utialization i am > only interrested in the worst case scenario. If we take Vccint for > example: > > 1.2V 5% tolerance - 2A max - 0.5ns risetimes > > Inorder for the voltage ripple to be under 5% for the bandwidth of > 0.35/0.5ns =3D 700Mhz, the impedance of the PDS must be below : > (1.2V*0.05)/2A =3D 0.03RLook up the specs on the caps for the parasitic L and R. Now you can build a spreadsheet that calculates the complex impedance Z as a function of frequency of each cap type (i.e. 10uF, 4.7uF, etc.). Knowing that, you can now compute the impedance of your PDS as a function of frequency as well. Then graph it and you'll see your expected impedance profile. You'll also want to factor in your PCB impedance as well, but start with the caps.> > I know that the previous calculations assumed that the current demand > for the harmonics were 2A for the entire bandwidth, but how does the > current relate to the harmonics of a signal transitions? if i got > 50Mhz swiching frequency will the current drop with 20db/decade, just > as the amplitude of the harmonics?I'm not sure where you're getting the 20dB/decade assumption since the drop would depend entirely on the characteristics of the functions being generated. If you could build a really good pseudo random generator set of outputs from the FPGA, then one would expect a roughly flat frequency response across the entire frequency band. Most real designs though are not terribly random and would have some rolloff but trying to take advantage of that in designing the power delivery for an unknown FPGA design might not be the best approach. By the way, going about figuring out the number and values of caps to use based on current demand and voltage ripple over a frequency range as you're doing is exactly the right approach. Don't forget about the PCB stackup though, closely spaced power/ground plane pairs supply the low impedance path that you'll need to connect up the caps (which are the source of charge for the load) with the load itself. This PCB impedance can be factored into that same spreadsheet model. Kevin Jennings
Reply by ●January 22, 20082008-01-22
Allan Herriman <allanherriman@hotmail.com> wrote:> On Tue, 22 Jan 2008 01:00:49 -0800 (PST), kislo > <kislo02@student.sdu.dk> wrote:> >... decoupling network ... > > .. i dont have the luxury of a software tool > > to help me simulate and analyse> The headers in your post suggest you are using Windows. That's good, > because you can download LTSpice and use that.> http://www.linear.com/designtools/software/switchercad.jspUsing LTSpice with wine on linux many times :-) -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply by ●January 22, 20082008-01-22
"Symon" <symon_brewer@hotmail.com> wrote> Hi Kim, > I've not got much time so here's a few pointers:- > > IMO, Xilinx publish excessive requirements which covers their arse if > anything should go wrong. Fair enough. However, you should know that it's > fairly difficult to get this wrong, indeed, some folks (not me!) on this > newsgroup apparently use very few bypass caps.I don't know what you mean by very few but, for the 1.2V VCCINT, I used 12 caps in my last big FPGA board ;-) For a Stratix II 180 1.2V decoupling, I have: 5 x 2.2�F LLM21 (under the FPGA) 4 x 10�F LLL31 (under the FPGA too) 2 x 100�F 1210 caps nearby 1 x 1500�F Tantalum cap farther. I'm pretty happy with that stuff. I have a glitch less than 30mV when the FPGA current goes from 2A to 25A in a few �s. http://search.murata.co.jp/Ceramy/CatalogAction.do?sHinnm=LLM0805-22X7S225M4&sNHinnm=LLM215C70G225ME11&sLang=en http://www.murata.co.jp/cgi-spara/freq.pl?file=llm21%2Fllm215c70g225me11.s2p&lang=en&gpartnum=LLM215C70G225ME11&min=1&freq=MHz&max=10000&dB=-100 I also put small coax connectors to be able to monitor the power rails at least for the prototypes: http://www.hirose.co.jp/cataloge_hp/e32124820.pdf> Free capacitor parameter stuff.:- > http://www.murata.com/designlib/mcsil/index.htmlI use that too.> Above a few 10's of MHz, all same sized caps have the same impedance. (See > murata thing above) Just use 0402 1uF for everything. One per pin is more > than enough. Make sure your board has a ground plane, try to use two vias > for each cap terminal. > > Here's some stuff on where to place your caps. > > http://www.sigcon.com/pubsIndex.htm#bypass%20capacitors > > Or, ignore that stuff, sooo 20th C. Better bypass here:- > http://www.x2y.com/IMHO the LLM21 are better ;-) Marc
Reply by ●January 22, 20082008-01-22
"Marc Battyani" <Marc.Battyani@fractalconcept.com> wrote in message news:19OdnZDlTN_j_QvanZ2dneKdnZydnZ2d@giganews.com...>> >> Or, ignore that stuff, sooo 20th C. Better bypass here:- >> http://www.x2y.com/ > > IMHO the LLM21 are better ;-) > > Marc > >Hi Marc, 25 amps? You madman! Anyway, if you get a spare moment, I'd appreciate you opinion of:- http://www.x2y.com/bypass/measure/comparative_decoupling.pdf pg. 16. They talk about "X2Y vs. Reverse Aspect Ratio Capacitors". I'm planning on going for X2Y on my next design, but I'd be interested in your analysis... Cheers, Syms.
