Virtex4: LVDS-Inputs in banks with VCCO!=2.5V (again)

Hi *,

since switching to ISE9.2, one of my favourite topics has come up
again... Basically, what I have is an FPGA with a bank that has a VCCO
of 3.3V. This bank has several LVTTL outputs and a few LVDS25-inputs. At
the time when the board was designed, this was a valid configuration:
LVDS-input buffers are powered from VCCAUX, which is always 2.5V, so it
doesn't matter what your VCCO on that bank is. ISE8.2, which was used at
the beginning of development, didn't even issue a warning here.

Starting with ISE9.1, par would stop with a FATAL_ERROR, because I was
using the DIFF_TERM-attribute on those LVDS-inputs, and it turns out
that even though the input buffers are powered from VCCAUX, the
termination is not, i.e. in the case where VCCO!=2.5V the termination
value is not 100 Ohms, but something else, unspecified. In my case it
didn't matter, everything works fine with that "wrong" termination as
well, and it turns out that there is some magical environment variable
you can set so par will just ignore this and finish its job.

Now I tried the design in ISE9.2, and it again fails (despite setting
the mentioned environment variable), this time issuing an error message
stating that LVDS-inputs cannot be put in the same bank as
LVTTL-outputs. This combination of IO standards is now forbidden completely.

Question is: Why?

Looking at the latest Virtex4 data sheet (ug070 2.3 from 8/10/2007, page
304, table 6-38), there is one footnote that was added 4 days after the
previous doc release. It says: "Differential inputs and inputs using
VREF are powered from VCCAUX. However, pin voltage must not exceed VCCO,
due to the presence of clamp diodes to VCCO.".

I don't quite see the relevance to my case here, but that's what changed
last...

cu,
Sean

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"Sean Durkin" <news_jan08@durkin.de> wrote in message 
news:603pbrF1p9i4dU1@mid.individual.net...
>
> Question is: Why?
>
Hi Sean,
It's because they're not clever enough to have one of your designs in their 
regression test suite. Perhaps you could donate them one? They clearly need 
it.

Please let us know how you resolve this, I've used this on designs also. 
ISTR I usually lie to it about the bank's VCCO.

As to why the chip designers didn't power the DIFF_TERM from VCCAUX, I'd 
like an answer to that.

Cheers, Syms. 

Symon wrote:
> Please let us know how you resolve this, I've used this on designs also. 
> ISTR I usually lie to it about the bank's VCCO.
OK, my bad, I take everything back. The line setting the magical 
environment variable PL_NO_SIO_DRC=1 was commented out in my synthesis 
script. So ISE was complaining about the DIFF_TERM-issue, just like 
before, not because of LVDS-IOs mixed with LVTTL-IOs. Still, the error 
message you get doesn't say anything about DIFF_TERM, just that LVDS 
inputs and LVTTL outputs cannot be mixed, which is a bit misleading...

But I found something new originating from changing documentation... I 
use some ISERDES-primitives as well, in NETWORKING-mode. Turns out that 
since ISE9.2 you can only use NETWORKING mode if you enable the bitslip 
mode (see AR #25507), otherwise you have to use MEMORY-mode. So I now 
have a design that runs through ISE8.2 without warnings, and fails in 
ISE9.2.
Works perfectly on the hardware, i.e. "real life". *IF* I can get it to
finish synthesizing, that is  :)

cu,
Sean

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