I wonder if it is possible to synthesize on one chip VHDL and Verilog IP cores. I suppose the VHDL to Verilog or vice versa translator could be used. Ideas are welcome. Remis -- ************************************************ To reply, remove >.spam< and >.fake<
Verilog and VHDL mix
Started by ●February 12, 2004
Reply by ●February 12, 20042004-02-12
Can't you do that with Synplify? If not, you can always synthesize blocks of, say, VHDL, separately and then instantiate them as EDIF black boxes in the Verilog design. -Kevin "Remis Norvilis" <Norvilis.spam@charter.net.fake> wrote in message news:102of4grl3t4n38@corp.supernews.com...> I wonder if it is possible to synthesize on one chip VHDL and Verilog IP > cores. I suppose the VHDL to Verilog or vice versa translator could be > used. > Ideas are welcome. > > Remis > -- > > ************************************************ > To reply, remove >.spam< and >.fake<
Reply by ●February 13, 20042004-02-13
You can usually do mixed language if you are prepared to pay lots of money for licenses. But if your doing Xilinx, or maybe something else, then have a look at the second method outlined here http://www.enterpoint.co.uk/techitips.html . You can synthesis with XST in both Verilog and VHDL. I can't confirm if you can do both at once in one project I would need to check that. If I was doing on a design that is big enough to warrant 2 languages I would usually break it down into some kind of increment / modular flow anyway. You can also use ISE toolset to write out a module in another language. It is there mainly for simulation but you can use it otherwise. John Adair Enterpoint Ltd. This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "Remis Norvilis" <Norvilis.spam@charter.net.fake> wrote in message news:102of4grl3t4n38@corp.supernews.com...> I wonder if it is possible to synthesize on one chip VHDL and Verilog IP > cores. I suppose the VHDL to Verilog or vice versa translator could be > used. > Ideas are welcome. > > Remis > -- > > ************************************************ > To reply, remove >.spam< and >.fake<
Reply by ●February 13, 20042004-02-13
Remis Norvilis <Norvilis.spam@charter.net.fake> writes:> I wonder if it is possible to synthesize on one chip VHDL and Verilog IP > cores. I suppose the VHDL to Verilog or vice versa translator could be > used. > Ideas are welcome.Current versions of Xilinx XST, Altera Quartus, and Synplify Pro all support mixed verilog/VHDL designs. David
Reply by ●February 15, 20042004-02-15
On Fri, 13 Feb 2004 09:26:44 -0000, "John Adair" <newsreply@loseinspace.co.uk> wrote:>You can usually do mixed language if you are prepared to pay lots of money >for licenses. But if your doing Xilinx, or maybe something else, then have a >look at the second method outlined here >http://www.enterpoint.co.uk/techitips.html . You can synthesis with XST in >both Verilog and VHDL. I can't confirm if you can do both at once in one >project I would need to check that.You can use both at once in the current version of XST. Regards, Allan.