Has anyone managed to get the xilinx BSCAN primitives (for interfacing with the USERx jtag registers/comands) working robustly? I've found a depressing lack of information as to what the actual pins do -- aside from a (now unavailable?) techXclusive article, "Reconfiguring Block RAMs - Part 1" (by Kris Chaplin, available via google cache) I can't find much more info. What's the best way to interface with this part? In particular, how do you deal with the obvious synchronization/metastability issues when crossing clock domains, esp. if you're hoping for a device that's still small (i.e. no hardware async fifos or anything). Thanks for any advice you can provide, ...Eric
Xilinx BSCAN primitives proper use
Started by ●January 31, 2008
Reply by ●January 31, 20082008-01-31
On Jan 31, 6:24 am, jo...@mit.edu wrote:> Has anyone managed to get the xilinx BSCAN primitives (for interfacing > with the USERx jtag registers/comands) working robustly? I've found a > depressing lack of information as to what the actual pins do -- aside > from a (now unavailable?) techXclusive article, "Reconfiguring Block > RAMs - Part 1" (by Kris Chaplin, available via google cache) I can't > find much more info. > > What's the best way to interface with this part? In particular, how do > you deal with the obvious synchronization/metastability issues when > crossing clock domains, esp. if you're hoping for a device that's > still small (i.e. no hardware async fifos or anything). > > Thanks for any advice you can provide, > ...EricI used it recently for the 1st time to check out a JTAG interface block I was developing. Here's the very simple code I used: // ---------------------------------------------------------------------- // Xilinx BSCAN // This is temporary code that allows us to test out JTAG master block by // using the Xilinx JTAG block reg [31:0] bscan_data; BSCAN_SPARTAN3 u_bscan ( .CAPTURE (BSCAN_CAPTURE), .DRCK1 (BSCAN_DRCK1), .DRCK2 (), .RESET (BSCAN_RESET), .SEL1 (BSCAN_SEL1), .SEL2 (), .SHIFT (BSCAN_SHIFT), .TDI (BSCAN_TDI), .UPDATE (BSCAN_UPDATE), .TDO1 (bscan_data[0]), .TDO2 (1'b0) ); always @(posedge BSCAN_DRCK1 or posedge BSCAN_RESET) if (BSCAN_RESET) bscan_data <= 32'h87654321; else if (BSCAN_SHIFT) bscan_data <= {BSCAN_TDI, bscan_data[31:1]}; The code provides access to a simple shift register. This would be simple to extend to a much more functional block, but as you point out, you'll need to take care of clock domain crossing, etc. John Providenza
Reply by ●February 1, 20082008-02-01
On Jan 31, 9:24 pm, johnp <johnp3+nos...@probo.com> wrote:> On Jan 31, 6:24 am, jo...@mit.edu wrote: > > > Has anyone managed to get the xilinx BSCAN primitives (for interfacing > > with the USERx jtag registers/comands) working robustly? I've found a > > depressing lack of information as to what the actual pins do -- aside > > from a (now unavailable?) techXclusive article, "Reconfiguring Block > > RAMs - Part 1" (by Kris Chaplin, available via google cache) I can't > > find much more info. > > > What's the best way to interface with this part? In particular, how do > > you deal with the obvious synchronization/metastability issues when > > crossing clock domains, esp. if you're hoping for a device that's > > still small (i.e. no hardware async fifos or anything). > > > Thanks for any advice you can provide, > > ...Eric > > I used it recently for the 1st time to check out a JTAG interface > block I > was developing. Here's the very simple code I used: > // > ---------------------------------------------------------------------- > // Xilinx BSCAN > // This is temporary code that allows us to test out JTAG master block > by > // using the Xilinx JTAG block > reg [31:0] bscan_data; > > BSCAN_SPARTAN3 u_bscan ( > .CAPTURE (BSCAN_CAPTURE), > .DRCK1 (BSCAN_DRCK1), > .DRCK2 (), > .RESET (BSCAN_RESET), > .SEL1 (BSCAN_SEL1), > .SEL2 (), > .SHIFT (BSCAN_SHIFT), > .TDI (BSCAN_TDI), > .UPDATE (BSCAN_UPDATE), > .TDO1 (bscan_data[0]), > .TDO2 (1'b0) > ); > > always @(posedge BSCAN_DRCK1 or posedge BSCAN_RESET) > if (BSCAN_RESET) > bscan_data <= 32'h87654321; > else if (BSCAN_SHIFT) > bscan_data <= {BSCAN_TDI, bscan_data[31:1]}; > > The code provides access to a simple shift register. This would be > simple > to extend to a much more functional block, but as you point out, > you'll > need to take care of clock domain crossing, etc. > > John ProvidenzaEric, Have you seen Gnat tool ? It is a powerful tool for communicating with FPGA through JTAG, consisting of a VHDL core and TCL scripts to establish the communication. Hope this helps, /MH
Reply by ●February 1, 20082008-02-01
On Feb 1, 3:13 am, mh <moazzamhuss...@gmail.com> wrote:> > Eric, > Have you seen Gnat tool ? > It is a powerful tool for communicating with FPGA through JTAG, > consisting of a VHDL core and TCL scripts to establish the > communication. > > Hope this helps, > /MHGnat looks like a very useful suite of tools. Unfortunately, the article (http://www.xilinx.com/publications/xcellonline/xcell_53/ xc_jtag53.htm) was written in 2005, and the URLs to the actual applications & libraries are all dead (the company that was hosting them has deleted them - searching the website turns up nothing). Nice idea though. Anyone know if the project has been moved somewhere else? EB
Reply by ●February 1, 20082008-02-01
On Fri, 1 Feb 2008 09:13:38 -0800 (PST), emeb <ebrombaugh@gmail.com> wrote:>On Feb 1, 3:13 am, mh <moazzamhuss...@gmail.com> wrote: >> >> Eric, >> Have you seen Gnat tool ? >> It is a powerful tool for communicating with FPGA through JTAG, >> consisting of a VHDL core and TCL scripts to establish the >> communication. >> >> Hope this helps, >> /MH > >Gnat looks like a very useful suite of tools. Unfortunately, the >article (http://www.xilinx.com/publications/xcellonline/xcell_53/ >xc_jtag53.htm) was written in 2005, and the URLs to the actual >applications & libraries are all dead (the company that was hosting >them has deleted them - searching the website turns up nothing). > >Nice idea though. Anyone know if the project has been moved somewhere >else? > >EBThere seems to be a copy here: http://www.xess.com/appnotes/gnat_xsa_3s1000.html
Reply by ●February 4, 20082008-02-04
On Feb 1, 11:12 pm, mk <kal*@dspia.*comdelete> wrote:> On Fri, 1 Feb 2008 09:13:38 -0800 (PST), emeb <ebromba...@gmail.com> > wrote: > > > > >On Feb 1, 3:13 am, mh <moazzamhuss...@gmail.com> wrote: > > >> Eric, > >> Have you seen Gnat tool ? > >> It is a powerful tool for communicating with FPGA through JTAG, > >> consisting of a VHDL core and TCL scripts to establish the > >> communication. > > >> Hope this helps, > >> /MH > > >Gnat looks like a very useful suite of tools. Unfortunately, the > >article (http://www.xilinx.com/publications/xcellonline/xcell_53/ > >xc_jtag53.htm) was written in 2005, and the URLs to the actual > >applications & libraries are all dead (the company that was hosting > >them has deleted them - searching the website turns up nothing). > > >Nice idea though. Anyone know if the project has been moved somewhere > >else? > > >EB > > There seems to be a copy here:http://www.xess.com/appnotes/gnat_xsa_3s1000.htmlAll, I myself was confronted with such a situation and I asked this question on this forum, and was contacted by S3 group who later sent me the tool. I used it and found it an excellent tool. HTH /MH
Reply by ●February 4, 20082008-02-04
> I myself was confronted with such a situation and I asked this> question on this forum, and was contacted by S3 group who later sent > me the tool. I used it and found it an excellent tool. > HTHSeems the unmodified tool is still missing on the S3 site: http://www.s3group.com/system_ic/gnat/download_gnat/ Could you upload it somewhere?
Reply by ●February 7, 20082008-02-07
On Feb 4, 7:22 pm, posedg...@yahoo.com wrote:> > I myself was confronted with such a situation and I asked this > > > question on this forum, and was contacted by S3 group who later sent > > me the tool. I used it and found it an excellent tool. > > HTH > > Seems the unmodified tool is still missing on the S3 site:http://www.s3group.com/system_ic/gnat/download_gnat/ > > Could you upload it somewhere?Hi, I had a correspondence with S-3 group and they allowed me to freely distribute Gnat tool with a comment that they don't support this tool any more. So, Any one who need this tool may contact me directly. /MH
Reply by ●February 17, 20082008-02-17
On Jan 31, 2:24=A0pm, jo...@mit.edu wrote:> Has anyone managed to get the xilinx BSCAN primitives (for interfacing > with the USERx jtag registers/comands) working robustly? I've found a > depressing lack of information as to what the actual pins =A0do -- aside > from a (now unavailable?) techXclusive article, "Reconfiguring Block > RAMs - Part 1" (by Kris Chaplin, available via google cache) I can't > find much more info. > > What's the best way to interface with this part? In particular, how do > you deal with the obvious synchronization/metastability issues when > crossing clock domains, esp. if you're hoping for a device that's > still small (i.e. no hardware async fifos or anything). > > Thanks for any advice you can provide, > =A0 =A0...EricIf you need a copy of this article - please let me know at chaplin <at> xilinx <dot> com Regards Kris
Reply by ●January 25, 20142014-01-25
On Wednesday, February 6, 2008 11:31:22 PM UTC-8, mh wrote:> On Feb 4, 7:22 pm, posedg...@yahoo.com wrote: > > > I myself was confronted with such a situation and I asked this > > > > > question on this forum, and was contacted by S3 group who later sent > > > me the tool. I used it and found it an excellent tool. > > > HTH > > > > Seems the unmodified tool is still missing on the S3 site:http://www.s3group.com/system_ic/gnat/download_gnat/ > > > > Could you upload it somewhere? > > > > Hi, > I had a correspondence with S-3 group and they allowed me to freely > distribute Gnat tool with a comment that they don't support this tool > any more. > > So, Any one who need this tool may contact me directly. > > /MH
