Simple Memory Read problem, help appreciated

Hi

I have a strange bug in my simulation and cant figure out the error.
I have a simple ram that contains data that should be read as described 
in the following process:

       PROC_ram : process (clk)
       begin
         if (clk'event and clk = '1') then
           -- memory write:
           if (ew_cp0 = '1') then
               ram(conv_integer(unsigned(rw_addr_cp0))) <= data_in_cp0;
             end if;
             if (rst = '0') then -- optional reset
             data_out_cp0 <= (others => '0');
              else
             data_out_cp0 <= ram(conv_integer(unsigned(rw_addr_cp0)));
              end if;
         end if;
     end process PROC_ram;

The problem that I have is, that the data is output with a delay of one 
cycle. So when I check the waveforms I see that on a rising edge of the
clock the address changes to one for instance, but the data is still 
read from memory position zero...

Anyone an idea what could be wrong here?

Many thanks!

Stupid me, I should have an asynchronous read....

Now it looks like this:

       PROC_ram : process (clk)
       begin
         if (clk'event and clk = '1') then
           -- memory write:
           if (ew_cp0 = '1') then
               ram(conv_integer(unsigned(rw_addr_cp0))) <= data_in_cp0;
             end if;
		    if (rst = '0') then -- optional reset
             --data_out_cp0 <= (others => '0');
			-- else
             --data_out_cp0 <= ram(conv_integer(unsigned(rw_addr_cp0)));
			 end if;
         end if;
     end process PROC_ram;
     data_out_cp0 <= ram(conv_integer(unsigned(rw_addr_cp0)));

In this case the reset port can be omitted, I wanna sythesis this as a 
BRAM on a Xilinx FPGA. Hope that works!

 > In this case the reset port can be omitted, I wanna sythesis this as a
 > BRAM on a Xilinx FPGA. Hope that works!

Well .. unfortuatnely XST tells me that the RAM will be implemented with 
LUTS and that I have to describe it in a way that BRAM can be 
instatiated, so that initial values can be stored in it...

Anyone who can help me out in this matter?

"Gerry" <Gerry@hotmail.com> wrote in message news:focaks$3r3$2@aioe.org...
>
> > In this case the reset port can be omitted, I wanna sythesis this as a
> > BRAM on a Xilinx FPGA. Hope that works!
>
> Well .. unfortuatnely XST tells me that the RAM will be implemented with 
> LUTS and that I have to describe it in a way that BRAM can be instatiated, 
> so that initial values can be stored in it...
>
> Anyone who can help me out in this matter?

Xilinx has templates for how to write code that will infer memory that can 
be implemented in ram blocks.  Check the documentation.

I'm guessing that the problem area might have to do with your reset section. 
Try taking out the entire 'if (rst = '0')....end if;' section of code and 
see if it infers the memory correctly.

Kevin Jennings 

KJ wrote:
> "Gerry" <Gerry@hotmail.com> wrote in message news:focaks$3r3$2@aioe.org...
>>> In this case the reset port can be omitted, I wanna sythesis this as a
>>> BRAM on a Xilinx FPGA. Hope that works!
>> Well .. unfortuatnely XST tells me that the RAM will be implemented with 
>> LUTS and that I have to describe it in a way that BRAM can be instatiated, 
>> so that initial values can be stored in it...
>>
>> Anyone who can help me out in this matter?
> 
> Xilinx has templates for how to write code that will infer memory that can 
> be implemented in ram blocks.  Check the documentation.
> 
> I'm guessing that the problem area might have to do with your reset section. 
> Try taking out the entire 'if (rst = '0')....end if;' section of code and 
> see if it infers the memory correctly.

Thanks Kevin, but the problem remains... Without the reset, the tool 
still tells me that when i have an asynchronous read and so BRAM cant be
used... I am using XST 7.3. Anyone a workaround for this problem?

Would be very much appreciated

"Gerry" <Gerry@hotmail.com> wrote in message news:focf2m$ij4$1@aioe.org...
> KJ wrote:

<snip>
> Thanks Kevin, but the problem remains... Without the reset, the tool still 
> tells me that when i have an asynchronous read and so BRAM cant be
> used...

Seems pretty clear to me...use a synchronous read

> I am using XST 7.3. Anyone a workaround for this problem?
>
> Would be very much appreciated

Once again, we call on that Spanish hero Manual

Per Xilinx's website

Templates for inferring registers, flip-flops, or memory can be found in 
Chapter 2 of the XST User Guide at:
http://www.xilinx.com/support/software_manuals.htm

Although a more useful link is
http://toolbox.xilinx.com/docsan/xilinx8/books/docs/xst/xst.pdf

Page 174...

Kevin Jennings 

I have posted here many times, and it is clearly descibed in the user
guide:
BlockRAM read is always a synchronous operation. There is no
asynchronous read in BlockRAM, no matter how hard you try, and how
much you desire it. It's inherent in the hardware design, no if, no
but.
LUT-RAM read is inherently asynchronous, but you can add a flip=3Dflop
tp make it synchronous.
Peter Alfke, Xilinx

On Feb 6, 6:09=A0am, Gerry <Ge...@hotmail.com> wrote:
> KJ wrote:
> > "Gerry" <Ge...@hotmail.com> wrote in messagenews:focaks$3r3$2@aioe.org..=
.
> >>> In this case the reset port can be omitted, I wanna sythesis this as a=

> >>> BRAM on a Xilinx FPGA. Hope that works!
> >> Well .. unfortuatnely XST tells me that the RAM will be implemented wit=
h
> >> LUTS and that I have to describe it in a way that BRAM can be instatiat=
ed,
> >> so that initial values can be stored in it...
>
> >> Anyone who can help me out in this matter?
>
> > Xilinx has templates for how to write code that will infer memory that c=
an
> > be implemented in ram blocks. =A0Check the documentation.
>
> > I'm guessing that the problem area might have to do with your reset sect=
ion.
> > Try taking out the entire 'if (rst =3D '0')....end if;' section of code =
and
> > see if it infers the memory correctly.
>
> Thanks Kevin, but the problem remains... Without the reset, the tool
> still tells me that when i have an asynchronous read and so BRAM cant be
> used... I am using XST 7.3. Anyone a workaround for this problem?
>
> Would be very much appreciated

Peter Alfke wrote:
> I have posted here many times, and it is clearly descibed in the user
> guide:
> BlockRAM read is always a synchronous operation. There is no
> asynchronous read in BlockRAM, no matter how hard you try, and how
> much you desire it. It's inherent in the hardware design, no if, no
> but.
> LUT-RAM read is inherently asynchronous, but you can add a flip=flop
> tp make it synchronous.
> Peter Alfke, Xilinx

Alright, thanks for the feedback peter. The problem is, that I need
an asynchronous read for the module I am using. So the problem is, that
I cant initialise the values in the RAM as in the BRAM.

Is there any other way to get initial values into the asynchronous RAM?
Does an upgrade to a newer version of XST help or am I doomed?

Thanks
G

Take a look at /Xilinx/doc/usenglish/docs/lib/lib.pdf.
Look up component RAM_16x1D.  There are examples on
setting the initial values of RAM.

More importantly, be familiar with the various
documents under the /docs/ subtree.  The developers
reference and constraint guide are equally invaluable.

-- 

Regards,
John Retta
Owner and Designer
Retta Technical Consulting Inc.

Colorado Based Xilinx Consultant

phone : 303.926.0068
email : jretta@rtc-inc.com
web   :  www.rtc-inc.com

John Retta wrote:
> Take a look at /Xilinx/doc/usenglish/docs/lib/lib.pdf.
> Look up component RAM_16x1D.  There are examples on
> setting the initial values of RAM.
> 
> More importantly, be familiar with the various
> documents under the /docs/ subtree.  The developers
> reference and constraint guide are equally invaluable.

THanks John, will have then a look at it. Just hope that
it also works with my old XST 7.1...