Simple Memory Read problem, help appreciated

Gerry <Gerry@hotmail.com> writes:

>> In this case the reset port can be omitted, I wanna sythesis this as a
>> BRAM on a Xilinx FPGA. Hope that works!
>
> Well .. unfortuatnely XST tells me that the RAM will be implemented
> with LUTS and that I have to describe it in a way that BRAM can be
> instatiated, so that initial values can be stored in it...
>

In which case you have to have the single clock latency that you
described - sorry - that's just the way BRAMs work.

Cheers,
Martin


-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

> In which case you have to have the single clock latency that you
> described - sorry - that's just the way BRAMs work.
> 

Yes, I am now using the Core generator to generate a distributed RAM 
with latency zero. Will be a little bit more painful, but hope to get
it working with initialising it. Obviously the sythesis will take a lot
of time and occupy a lot of logic but this I will accept now for a test!

Maybe I have to rethink and rewrite the design to be conform with 
sychronous BRAM!