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Partial Reconfiguration of Virtex-5: ISE and EAPR?

Started by kyprianos February 6, 2008
Hi all,

Does anyone know whether Virtex-5 devices are supported by the Partial
Reconfiguration design flow. I understand that PlanAhead supports it
but which versions of the ISE and the EAPR support partial
reconfiguration for Virtex-5?

Thanx
kyprianos
Kyprianos,

Have you read:

http://www.xilinx.com/products/design_tools/logic_design/advanced/partial_reconf_faq.htm

?

All Virtex parts (original through V5) "support" partial reconfiguration
(able to load new partial bitstreams while continuing to run) in
hardware. Is your question more one of what tools and what is the
recommended flow?

Austin
Hi Kyprianos,

Your best bet will be to go for EAPR with ISE 9.1i SP2. I do research
in partial reconfiguration and when I was at a Xilinx Partial
Reconfiguration workshop in TU Delft in the Netherlands last year, the
Xilinx presenter alluded to the fact that Virtex-5 FPGAs are being
supported in 9.1i.

PlanAhead is the front-end to EAPR and ISE, so all it really does it
give you a graphical, user-friendly interface, generate the
constraints files and execute the tools for you rather than using your
own scripts.

Austin, thanks for your reply and I believe Kyprianos did ask if which
versions of the ISE and EAPR tools support Virtex-5. Apart from that,
I do believe that the old Virtex (first generation) family does have
some problems regarding glitchless reconfiguration? It would be great
to talk to you to obtain more definitive answers from Xilinx! Were you
at TU Delft (FPL2007) last August?

Cheers,
Shannon

On Feb 7, 4:25 am, austin <aus...@xilinx.com> wrote:
> Kyprianos, > > Have you read: > > http://www.xilinx.com/products/design_tools/logic_design/advanced/par... > > ? > > All Virtex parts (original through V5) "support" partial reconfiguration > (able to load new partial bitstreams while continuing to run) in > hardware. Is your question more one of what tools and what is the > recommended flow? > > Austin
On Feb 7, 2:39 am, shac...@gmail.com wrote:
> Hi Kyprianos, > > Your best bet will be to go for EAPR with ISE 9.1i SP2. I do research > in partial reconfiguration and when I was at a Xilinx Partial > Reconfiguration workshop in TU Delft in the Netherlands last year, the > Xilinx presenter alluded to the fact that Virtex-5 FPGAs are being > supported in 9.1i. > > PlanAhead is the front-end to EAPR and ISE, so all it really does it > give you a graphical, user-friendly interface, generate the > constraints files and execute the tools for you rather than using your > own scripts. > > Austin, thanks for your reply and I believe Kyprianos did ask if which > versions of the ISE and EAPR tools support Virtex-5. Apart from that, > I do believe that the old Virtex (first generation) family does have > some problems regarding glitchless reconfiguration? It would be great > to talk to you to obtain more definitive answers from Xilinx! Were you > at TU Delft (FPL2007) last August? > > Cheers, > Shannon > > On Feb 7, 4:25 am, austin <aus...@xilinx.com> wrote: > > > Kyprianos, > > > Have you read: > > >http://www.xilinx.com/products/design_tools/logic_design/advanced/par... > > > ? > > > All Virtex parts (original through V5) "support" partial reconfiguration > > (able to load new partial bitstreams while continuing to run) in > > hardware. Is your question more one of what tools and what is the > > recommended flow? > > > Austin
Hi all, Austin and Shannon thank you for the reply. It is clear that Virtex-5 architecture does support partial reconfiguration. My question was more about the tools. Which versions of the ISE and EAPR - as well as of EDK for self-reconfiguration with a uP - are needed to partially reconfigure a Virtex-5? I understand that partial reconfiguration becomes less painfull with the use of PlanAhead. Although someone can proceed without it. In the Xilinx's website, Section "Partial Reconfiguration Early Access software tools for ISE 8.2i SP1" (http://www.xilinx.com/support/ prealounge/protected/archive_82.htm), it is mentioned that "These software tools only support the Virtex(tm)-4, Virtex-II and Virtex-II Pro architectures. They must be installed on top of the ISE(tm) 8.2i sp1 release.". There is nothing reported regarding Virtex-5 and recent versions of ISE, e.g. can 9.1.2i EDK + 9.1i ISE w/ SP3 + EAPR be used to apply self-PR on the Virtex-5? Is there any reference design that I can get? Kyprianos
Shannon,

My email is good (austin@xilinx.com).

As for 'old' Virtex (220nm), I seem to recall something, but that is
ancient history now.  If anyone is using Virtex for their research, they
should contact the XUP and get some new parts!

Austin
Kyprianos,

All I know about software, is that the versions MUST match (IE 9.1 ISE +
9.1 EDK is OK, but 9.1 ISE + 9.2 EDK IS NOT OK!).

Yes, Virtex 5 has been out for 18 months now, with the LX, LXT, SXT all
in production, so there are even older versions (ie 8.x) that support
V5, and hence, partial reconfiguration.

I always recommend starting any new project with the latest release of
software so as to take advantage of all of the bug fixes (without having
to load service packs).

The next best choice is to use the immediate previous version, with all
service packs.  This is just the "way of software" and really has
nothing to do with Xilinx:  the latest version inevitably has some new
bugs, and the immediate previous version is usually the best possible
choice for software that has the fewest unknown, or unfixed behaviors.

The newest version has all the resources going to fix things in the
shortest time.  The previous version has had perhaps 100,000 users
banging on it for 6 months or more.

Austin
Hi Kyprianos,

Have you tried 9.1SP2 with EAPR? Don't use the 8.2i archive, simply go
to:

http://www.xilinx.com/support/prealounge/protected/index.htm

As the website says: "These software tools only support the Virtex-5,
Virtex(tm)-4, Virtex-II and Virtex-II Pro architectures.", so I believe
9.1SP2 will work with the Virtex-5.

In any case, give it a go.

Shannon

On Feb 8, 1:48 am, kyprianos <kpapa...@mhl.tuc.gr> wrote:
> On Feb 7, 2:39 am, shac...@gmail.com wrote: > > > > > > > Hi Kyprianos, > > > Your best bet will be to go for EAPR with ISE 9.1i SP2. I do research > > in partial reconfiguration and when I was at a Xilinx Partial > > Reconfiguration workshop in TU Delft in the Netherlands last year, the > > Xilinx presenter alluded to the fact that Virtex-5 FPGAs are being > > supported in 9.1i. > > > PlanAhead is the front-end to EAPR and ISE, so all it really does it > > give you a graphical, user-friendly interface, generate the > > constraints files and execute the tools for you rather than using your > > own scripts. > > > Austin, thanks for your reply and I believe Kyprianos did ask if which > > versions of the ISE and EAPR tools support Virtex-5. Apart from that, > > I do believe that the old Virtex (first generation) family does have > > some problems regarding glitchless reconfiguration? It would be great > > to talk to you to obtain more definitive answers from Xilinx! Were you > > at TU Delft (FPL2007) last August? > > > Cheers, > > Shannon > > > On Feb 7, 4:25 am, austin <aus...@xilinx.com> wrote: > > > > Kyprianos, > > > > Have you read: > > > >http://www.xilinx.com/products/design_tools/logic_design/advanced/par... > > > > ? > > > > All Virtex parts (original through V5) "support" partial reconfiguration > > > (able to load new partial bitstreams while continuing to run) in > > > hardware. Is your question more one of what tools and what is the > > > recommended flow? > > > > Austin > > Hi all, > > Austin and Shannon thank you for the reply. It is clear that Virtex-5 > architecture does support partial reconfiguration. My question was > more about the tools. Which versions of the ISE and EAPR - as well as > of EDK for self-reconfiguration with a uP - are needed to partially > reconfigure a Virtex-5? I understand that partial reconfiguration > becomes less painfull with the use of PlanAhead. Although someone can > proceed without it. > > In the Xilinx's website, Section "Partial Reconfiguration Early Access > software tools for ISE 8.2i SP1" (http://www.xilinx.com/support/ > prealounge/protected/archive_82.htm), it is mentioned that "These > software tools only support the Virtex(tm)-4, Virtex-II and Virtex-II Pro > architectures. They must be installed on top of the ISE(tm) 8.2i sp1 > release.". There is nothing reported regarding Virtex-5 and recent > versions of ISE, e.g. can 9.1.2i EDK + 9.1i ISE w/ SP3 + EAPR be used > to apply self-PR on the Virtex-5? Is there any reference design that I > can get? > > Kyprianos- Hide quoted text - > > - Show quoted text -
On Feb 7, 5:22 pm, austin <aus...@xilinx.com> wrote:
> Shannon, > > My email is good (aus...@xilinx.com). > > As for 'old' Virtex (220nm), I seem to recall something, but that is > ancient history now. If anyone is using Virtex for their research, they > should contact the XUP and get some new parts! > > Austin
Shannon and Austin, I will go through the new archive. Thank you both! Greetings, Kyprianos