I have a question about a conversion of an unsigned 10-bit vector to signed 8 bit vector. What is the best : signed_data(7 downto 0) <= STD_LOGIC_VECTOR(to_signed(to_integer(unsigned(unsigned_data)), 8)); or if ( unsigned_data = "00000000" ) then signed_data <= "10000001"; else signed_data <= (not unsigned_data(9)) & unsigned_data(8 downto 0); end if; tk.
Unsigned to signed vector.
Started by ●February 11, 2008
Reply by ●February 11, 20082008-02-11
"LilacSkin" <lpaulo07@iseb.fr> wrote in message news:6f2aa7d9-1627-46e8-b67e-423491be6791@i12g2000prf.googlegroups.com...>I have a question about a conversion of an unsigned 10-bit vector to > signed 8 bit vector. > What is the best : > > tk.http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf
Reply by ●February 11, 20082008-02-11
On 11 Feb., 12:48, LilacSkin <lpaul...@iseb.fr> wrote:> I have a question about a conversion of an unsigned 10-bit vector to > signed 8 bit vector.u(7) <= '0'; u(6 downto 0) <= s(6 downto 0); Kolja Sulimma
Reply by ●February 11, 20082008-02-11
On 11 f=E9v, 13:46, "comp.arch.fpga" <ksuli...@googlemail.com> wrote:> On 11 Feb., 12:48, LilacSkin <lpaul...@iseb.fr> wrote: > > > I have a question about a conversion of an unsigned 10-bit vector to > > signed 8 bit vector. > > u(7) <=3D '0'; > u(6 downto 0) <=3D s(6 downto 0); > > Kolja Sulimmaunsigned =3D> signed
Reply by ●February 11, 20082008-02-11
On Mon, 11 Feb 2008 04:46:52 -0800 (PST), "comp.arch.fpga" <ksulimma@googlemail.com> wrote:>On 11 Feb., 12:48, LilacSkin <lpaul...@iseb.fr> wrote: >> I have a question about a conversion of an unsigned 10-bit vector to >> signed 8 bit vector. > >u(7) <= '0'; >u(6 downto 0) <= s(6 downto 0);(where 's' is the 10-bit unsigned source, and 'u' is the 8-bit unsigned target, presumably.) Or, if you want saturating behaviour instead of truncation: signed_8(7) <= '0'; if unsigned_10(9 downto 7) = "000" then --- within range, 7 least-significant bits are OK signed_8(6 downto 0) <= unsigned_10(6 downto 0); else --- over-range, saturate to largest possible value signed_8(6 downto 0) <= (others => '1'); end if; -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
Reply by ●February 11, 20082008-02-11
What I want to do is : unsigned min: 0000000000 => signed min: 1 000001 => integer min : -127 unsigned max: 1111111111 => signed max: 0 1111111 => integer max : 127
Reply by ●February 11, 20082008-02-11
On Mon, 11 Feb 2008 05:06:54 -0800 (PST), LilacSkin <lpaulo07@iseb.fr> wrote:>What I want to do is : > >unsigned min: 0000000000 => signed min: 1 000001 => integer min : >-127 >unsigned max: 1111111111 => signed max: 0 1111111 => integer max : 127You didn't tell us that :-) Do you also want linear scaling between these two endpoints? I guess so. Let's start again. You have unsigned input U in the range [0,1023]. You have signed output S in the range [-127, +127]. I don't know why you choose to exclude -128, but hey, that's OK. So what do you want to do? S = U/4 - 127 is pretty close, I think, if U/4 is taken to mean the whole-number part of the result (throw away the fraction). But unfortunately, 1020/4 = 255 and 255-127 = 128, so you'll get +128 rather than +127 as the upper limit. If you can accept -128 as the lower limit (this is the true minimum value of a signed 8-bit) then you can do S = U/4 - 128 and all is well. Now, U/4 is simply the eight most significant bits of U; and -128 is easily done by just flipping the MSB; so S <= (not U(9)) & U(8 downto 2); will do the job. Now will you finally listen to your tutors and understand that THE MOST IMPORTANT THING IS A GOOD SPECIFICATION? -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
Reply by ●February 11, 20082008-02-11
On 11 f=E9v, 14:44, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote:> On Mon, 11 Feb 2008 05:06:54 -0800 (PST), > > LilacSkin <lpaul...@iseb.fr> wrote: > >What I want to do is : > > >unsigned min: 0000000000 =3D> signed min: 1 000001 =3D> integer min : > >-127 > >unsigned max: 1111111111 =3D> signed max: 0 1111111 =3D> integer max : 12=7> > You didn't tell us that :-) > > Do you also want linear scaling between these two endpoints? > I guess so. Let's start again. > > You have unsigned input U in the range [0,1023]. > > You have signed output S in the range [-127, +127]. > I don't know why you choose to exclude -128, but hey, > that's OK. > > So what do you want to do? > > S =3D U/4 - 127 > > is pretty close, I think, if U/4 is taken to mean the > whole-number part of the result (throw away the fraction). > But unfortunately, 1020/4 =3D 255 and 255-127 =3D 128, so you'll > get +128 rather than +127 as the upper limit. If you can > accept -128 as the lower limit (this is the true minimum > value of a signed 8-bit) then you can do > > S =3D U/4 - 128 > > and all is well. Now, U/4 is simply the eight most significant > bits of U; and -128 is easily done by just flipping the MSB; so > > S <=3D (not U(9)) & U(8 downto 2); > > will do the job. > > Now will you finally listen to your tutors and understand > that THE MOST IMPORTANT THING IS A GOOD SPECIFICATION? > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated.so, I return to my first message, that is correct : if ( unsigned_data =3D "00000000" ) then signed_data <=3D "10000001"; else signed_data <=3D (not unsigned_data(9)) & unsigned_data(8 downto 0); end if;
Reply by ●February 11, 20082008-02-11
On Mon, 11 Feb 2008 05:48:16 -0800 (PST), LilacSkin <lpaulo07@iseb.fr> wrote:>so, I return to my first message, that is correct :No, it's not; you're being unacceptably careless.>if ( unsigned_data = "00000000" ) thenThis test will never be true, because unsigned_data is 10 bits wide and can never be equal to an 8-bit vector.> signed_data <= "10000001"; >else > signed_data <= (not unsigned_data(9)) & > unsigned_data(8 downto 0);And now you're trying to copy a 10-bit expression into an 8-bit result. But yes, you're on the right track. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
Reply by ●February 12, 20082008-02-12
