Hello all, You have a snapshot of the XiRisc softcore processor sources ? It seems that sources are not available to download now anywhere ... Best regards.
XiRisc softcore processor
Started by ●February 12, 2008
Reply by ●February 12, 20082008-02-12
On 12 Feb., 18:10, "Jean-s=E9bastien LEROY" <jean.sebastien.le...@club- internet.fr> wrote:> Hello all, > > You have a snapshot of the XiRisc softcore processor sources ? > > It seems that sources are not available to download now anywhere ... > > Best regards.where was it supposedly been seen ?? Antti
Reply by ●February 12, 20082008-02-12
On Feb 12, 7:10 pm, "Jean-s=E9bastien LEROY" <jean.sebastien.le...@club- internet.fr> wrote:> Hello all, > > You have a snapshot of the XiRisc softcore processor sources ? > > It seems that sources are not available to download now anywhere ... > > Best regards.Hi indeed the XiRisc website has been down for more than a year. I believe what you need would be: 1. The VHDL source code distro. I have two different versions of this, one with a few more features (caches and an AMBA interface) and another one. (<1MB) 2. I have 4 different versions of the Xirisc gcc-based toolchain. The toolchain includes some additional "profiling" tools as well. (~30-50MB) 3. A set of nice (and mostly self-contained) benchmark programs. (~4MB) Which ones are OK to you? Do you need a toolchain as well? I can have a look on some ol' archives since 2002-2004 around my home PC. Will be there in a few hours (now i'm in the office). Kind regards Nikolaos Kavvadias PS1: Xirisc is nice and rather complete soft-core. Have used this for a couple of research publications. It is probably a little large for a small FPGA (200k system gates). If stripped, i believe it can fit in a S3E500. PS2: Fabio Campi and most of the Xirisc people might be around. You could ask them as well, on the status of Xirisc, the level of support etc.
Reply by ●February 12, 20082008-02-12
> > You have a snapshot of the XiRisc softcore processor sources ? > > where was it supposedly been seen ?? > > AnttiHi Antti it was distributed by the University of Bologna. It is overall a good work, yet unsupported for the last 2 or 3 years. The main page (there was a mirror at unibo too) are down for about a year or so. Kind regards Nikolaos Kavvadias
Reply by ●February 12, 20082008-02-12
The Xirisc forms the base of some ST commercial products. The Picoga 2D reconfigurable array, part of the products (i believe) is not distributed with the public VHDL source codes. I have used XiRisc (without Picoga) for a proof-of-concept architecture of a zero-overhead loop controller (ZOLC), embeddable to single-issue RISCs (like most soft-cores are). The ZOLC is placed in the instruction fetch stage of the processor, and totally removes the need for looping-related operations (index increment/decrement, comparison and branch) for static and quasi-static (known during run- time, but not compile-time) loop structures involving non-perfect nesting of loops. The work has been just published in the IEEE Trans. on Computers: N. Kavvadias and S. Nikolaidis Elimination of Overhead Operations in Complex Loop Structures for Embedded Microprocessors http://ieeexplore.ieee.org/iel5/12/4419570/04358242.pdf?isnumber=4419570&prod=JNL&arnumber=4358242&arSt=200&ared=214&arAuthor=Kavvadias%2C+Nikolaos%3B+Nikolaidis%2C+Spiridon Kind regards Nikolaos Kavvadias
Reply by ●February 12, 20082008-02-12
The Xirisc forms the base of some ST commercial products. The Picoga 2D reconfigurable array, part of the products (i believe) is not distributed with the public VHDL source codes. I have used XiRisc (without Picoga) for a proof-of-concept architecture of a zero-overhead loop controller (ZOLC), embeddable to single-issue RISCs (like most soft-cores are). The ZOLC is placed in the instruction fetch stage of the processor, and totally removes the need for looping-related operations (index increment/decrement, comparison and branch) for static and quasi-static (known during run- time, but not compile-time) loop structures involving non-perfect nesting of loops. The work has been just published in the IEEE Trans. on Computers: N. Kavvadias and S. Nikolaidis Elimination of Overhead Operations in Complex Loop Structures for Embedded Microprocessors http://ieeexplore.ieee.org/iel5/12/4419570/04358242.pdf?isnumber=4419570&prod=JNL&arnumber=4358242&arSt=200&ared=214&arAuthor=Kavvadias%2C+Nikolaos%3B+Nikolaidis%2C+Spiridon Kind regards Nikolaos Kavvadias
Reply by ●February 12, 20082008-02-12
The Xirisc forms the base of some ST commercial products. The Picoga 2D reconfigurable array, part of the products (i believe) is not distributed with the public VHDL source codes. I have used XiRisc (without Picoga) for a proof-of-concept architecture of a zero-overhead loop controller (ZOLC), embeddable to single-issue RISCs (like most soft-cores are). The ZOLC is placed in the instruction fetch stage of the processor, and totally removes the need for looping-related operations (index increment/decrement, comparison and branch) for static and quasi-static (known during run- time, but not compile-time) loop structures involving non-perfect nesting of loops. The work has been just published in the IEEE Trans. on Computers: N. Kavvadias and S. Nikolaidis Elimination of Overhead Operations in Complex Loop Structures for Embedded Microprocessors http://ieeexplore.ieee.org/iel5/12/4419570/04358242.pdf?isnumber=4419570&prod=JNL&arnumber=4358242&arSt=200&ared=214&arAuthor=Kavvadias%2C+Nikolaos%3B+Nikolaidis%2C+Spiridon Kind regards Nikolaos Kavvadias
Reply by ●February 12, 20082008-02-12
The Xirisc forms the base of some ST commercial products. The Picoga 2D reconfigurable array, part of the products (i believe) is not distributed with the public VHDL source codes. I have used XiRisc (without Picoga) for a proof-of-concept architecture of a zero-overhead loop controller (ZOLC), embeddable to single-issue RISCs (like most soft-cores are). The ZOLC is placed in the instruction fetch stage of the processor, and totally removes the need for looping-related operations (index increment/decrement, comparison and branch) for static and quasi-static (known during run- time, but not compile-time) loop structures involving non-perfect nesting of loops. The work has been just published in the IEEE Trans. on Computers: N. Kavvadias and S. Nikolaidis Elimination of Overhead Operations in Complex Loop Structures for Embedded Microprocessors http://ieeexplore.ieee.org/iel5/12/4419570/04358242.pdf?isnumber=4419570&prod=JNL&arnumber=4358242&arSt=200&ared=214&arAuthor=Kavvadias%2C+Nikolaos%3B+Nikolaidis%2C+Spiridon Kind regards Nikolaos Kavvadias
Reply by ●February 12, 20082008-02-12
The Xirisc forms the base of some ST commercial products. The Picoga 2D reconfigurable array, part of the products (i believe) is not distributed with the public VHDL source codes. I have used XiRisc (without Picoga) for a proof-of-concept architecture of a zero-overhead loop controller (ZOLC), embeddable to single-issue RISCs (like most soft-cores are). The ZOLC is placed in the instruction fetch stage of the processor, and totally removes the need for looping-related operations (index increment/decrement, comparison and branch) for static and quasi-static (known during run- time, but not compile-time) loop structures involving non-perfect nesting of loops. The work has been just published in the IEEE Trans. on Computers: N. Kavvadias and S. Nikolaidis Elimination of Overhead Operations in Complex Loop Structures for Embedded Microprocessors http://ieeexplore.ieee.org/iel5/12/4419570/04358242.pdf?isnumber=4419570&prod=JNL&arnumber=4358242&arSt=200&ared=214&arAuthor=Kavvadias%2C+Nikolaos%3B+Nikolaidis%2C+Spiridon Kind regards Nikolaos Kavvadias
Reply by ●February 12, 20082008-02-12
