Define the primary clock with XST in VHDL

Hello Guys,

How to specify with XST that an input of a VHDL entity is a clock ?

I guess it is not automatic because after the XST logic synthesis,
noone of my "process" have been synthetized ?

thanks, Julien

On Feb 18, 9:17=A0am, Julien Lochen <loc...@noos.fr> wrote:
> Hello Guys,
>
> How to specify with XST that an input of a VHDL entity is a clock ?
>
> I guess it is not automatic because after the XST logic synthesis,
> noone of my "process" have been synthetized ?
>
> thanks, Julien

Use a simulator to verify correct functional operation of your top
level design...after that you should find that XST synthesizes your
design properly.

KJ

Julien Lochen wrote:

> How to specify with XST that an input of a VHDL entity is a clock ?
> I guess it is not automatic because after the XST logic synthesis,
> noone of my "process" have been synthetized ?


XST or quartus synthesis will find the clock in
vhdl code that matches a synchronous process template.
There are many ways to do this.
Here's one:

architecture synth of sync_template is
begin
   sync_template : process(reset, clock) is
  -- <declarations go here>
  begin  -- process template
      if reset = '1' then
         init_regs; -- init code here
      elsif rising_edge(clock) then
         update_regs; -- update code here
      end if;
      update_ports;   -- port assignments here
   end process sync_template;
end architecture synth;

details here:
http://home.comcast.net/~mike_treseler/

    -- Mike Treseler