Using Lattice ispLEVER with VHDL libraries

troy.scott@latticesemi.com wrote:

> There is no user-
> defined file order 7.0. It will attempt to build an ordered file list
> automatically. I have seen some VHDL designs fail under 7.0 that
> requires Service Pack 2 to correct.

This is a hard problem for vhdl even with a single work library.
I would recommend letting the user edit the order you come up with.
Otherwise, the trial-and-error method (which always works) is ruled out.

> We are working on this area to make it closer to the conventions you'd
> find in other EDA tools.

Don't stop trying, but note that I wasn't picking on Lattice.
I don't think any device vendor has
a front end that can do it all for complex projects.


       -- Mike Treseler

On Feb 25, 12:36 pm, troy.sc...@latticesemi.com wrote:
> Gents,
>
> Saw this thread go by on my alert list and wanted to check in.
>
> From the perspective of the synthesis and simulator, the Project
> Navigator's job is to supply an ordered file list, command line flags,
> and in some cases a script to automate a run.  There is no user-
> defined file order 7.0. It will attempt to build an ordered file list
> automatically. I have seen some VHDL designs fail under 7.0 that
> requires Service Pack 2 to correct.
>
> If all else fails, manage HDL source from within Synplify or Precision
> and create an EDIF-based ispLEVER project.
>
> It's accurate to say Project Navigator has some non-standard
> conventions for HDL file management. I blame it partially because
> system has a long history of managing all sorts of non-HDL file
> formats like schematic, ABEL, and the native Lattice parameter
> constraints file (LPC) created by IPexpress. Under the hood 7.0 is a
> big improvement over 6.x, it has far better capacity, performance, and
> language compliance when dealing with long file lists. It also
> supports mixing VHDL and Verilog.
>
> We are working on this area to make it closer to the conventions you'd
> find in other EDA tools.
>
> Troy Scott
> Software Marketing
> Lattice Semiconductor Corporation

Troy,

Thanks for replying.  I didn't get much from Lattice email support,
but the local FAE, Jon Rook, helped me out.  I guess the turn around
time for Jon is a lot better than the support folks.  By the time
support got around to asking me for my source files, Joh had the
problem figured out.  Seems that 7.0 is pretty new, I believe just
this month right?  Well I was using a version I had downloaded back in
November when I had first considered using a Lattice part.  The LFXP3
in the 100 pin TQFP is pretty well locked in unless I find something
unworkable in the next week or so.

The problem was just that 6.0 doesn't support user libraries.  Seems
there is no way to tell the software that you have one.  Version 7.0
lets me tell it what the libraries are and does figure out correctly
what order to compile the files.  The Xilinx and I think the Altera
tools allow (require?) you to specify the compile order.  I don't mind
that as it is done just once and is easy to do.  Hopefully the Lattice
tool will continue to work correctly as I add more modules.

I am having a little trouble figuring out the clocking capabilities.
I found info on the DCS clock mux.  That is just what I needed.  I
can't tell however, if two of them can be used to combine three
clocks.  I think I will be ok with just two clock inputs, but I'm not
sure.  My customer is getting good at throwing curves at me.  Good
thing I duck well!

I will also comment that Lattice makes it harder to try out their
products.  I am used to getting loans of eval boards and complete
evaluation software.  Lattice is requiring a formal 30 day agreement
with a PO.  I have never had that with Altera or Xilinx.