Hi I just came across some interview questions for digital design, and would like to discuss my solutions with you! #Design a circuit to divide input frequency by 2 I could do this with a Toggle Flip flop where the inverted output is connected to the input, then i also divide the clock frequency by two # Design a divide-by-3/divide-by-5 sequential circuit with 50% duty cycle. I was thinking of having here a statemachine that outputs for 3 cycles 0, and then it changes the state to output 3 times a 1 at each clock transition. # Which one is superior: Asynchronous Reset or Synchronous Reset Well, until now I was always using asynchronous resets because u find it in most textbooks ;) not so sure about the right answer here!
Interview questions
Started by ●February 21, 2008
Reply by ●February 21, 20082008-02-21
Clemens Blank schrieb:> Interview questionsand the best one I came across was to double the clock frequency. How on earth should this be possible, must be a trap!
Reply by ●February 21, 20082008-02-21
Clemens Blank wrote:> Clemens Blank schrieb: >> Interview questions > > and the best one I came across was to double the clock frequency. How on > earth should this be possible, must be a trap!For the question about dividing the frequency by two, be sure to note that you wouldn't use the resulting output as a (gated) clock! To double a frequency the best method is to use a PLL, but this requires some analog components. A DLL works well, but is jittery. A simple dirty method requires just an XOR and a delay element, but that's not a good synchronous design practice. -Kevin
Reply by ●February 21, 20082008-02-21
On Feb 21, 2:26=A0pm, Clemens Blank <CBl...@hotmail.com> wrote: <snip>> > # Design a divide-by-3/divide-by-5 sequential circuit with 50% duty cycle.=> I was thinking of having here a statemachine that outputs for 3 cycles > 0, and then it changes the state to output 3 times a 1 at each clock > transition. ><snip> Having a state machine with three high states followed by 3 low states is a divide by 6, not a divide by 3! The trick here to getting a 50% duty cycle output is to know that you need the positive edge of the incoming clock to control the rising edge of the output clock and the negative edge to control the falling (or vice-versa). This assumes, of course, that the input clock is 50%. Since most registers can't toggle on both posedge clk and negedge clock in the same flop, the output has to be a combinatorial result from the two edge domains. - John_H
Reply by ●February 22, 20082008-02-22
On Feb 22, 9:34=A0am, John_H <newsgr...@johnhandwork.com> wrote:> On Feb 21, 2:26=A0pm, Clemens Blank <CBl...@hotmail.com> wrote: > <snip> > > > # Design a divide-by-3/divide-by-5 sequential circuit with 50% duty cycl=e.> > I was thinking of having here a statemachine that outputs for 3 cycles > > 0, and then it changes the state to output 3 times a 1 at each clock > > transition. > > <snip> > > Having a state machine with three high states followed by 3 low states > is a divide by 6, not a divide by 3! > > The trick here to getting a 50% duty cycle output is to know that you > need the positive edge of the incoming clock to control the rising > edge of the output clock and the negative edge to control the falling > (or vice-versa). =A0This assumes, of course, that the input clock is > 50%. > > Since most registers can't toggle on both posedge clk and negedge > clock in the same flop, the output has to be a combinatorial result > from the two edge domains. > > - John_HAbout clock divider http://www.onsemi.com/pub/Collateral/AND8001-D.PDF
Reply by ●February 22, 20082008-02-22
I ran a series of posts on this: http://asicdigitaldesign.wordpress.com/2007/07/09/the-ultimate-interview-question-for-logic-design-a-mini-challenge/ http://asicdigitaldesign.wordpress.com/2008/01/24/ultimate-technical-interview-question-the-standard-solution/ http://asicdigitaldesign.wordpress.com/2008/01/31/ultimate-technical-interview-question-take-2/ hope this helps. I also have in my blog a full section on interview questions and puzzles: http://asicdigitaldesign.wordpress.com/category/interview-questions/ http://asicdigitaldesign.wordpress.com/category/puzzles/ hope this helps. Nir
Reply by ●February 22, 20082008-02-22
> # Which one is superior: Asynchronous Reset or Synchronous Reset > > Well, until now I was always using asynchronous resets because u > find it in most textbooks ;) not so sure about the right answer here!Depends upon what your criteria of superior is. Cheers, Jon
Reply by ●February 22, 20082008-02-22
On Feb 21, 10:33 pm, Clemens Blank <CBl...@hotmail.com> wrote:> Clemens Blank schrieb: > > > Interview questions > > and the best one I came across was to double the clock frequency. How on > earth should this be possible, must be a trap!An easy answer is to use a DCM in Virtex FPGA ... :-) haha details, as said, PLL and DLL...
Reply by ●February 22, 20082008-02-22
On Feb 22, 6:52 pm, "jack.harv...@googlemail.com" <jack.harv...@googlemail.com> wrote:> On Feb 21, 10:33 pm, Clemens Blank <CBl...@hotmail.com> wrote: > > > Clemens Blank schrieb: > > > > Interview questions > > > and the best one I came across was to double the clock frequency. How on > > earth should this be possible, must be a trap! > > An easy answer is to use a DCM in Virtex FPGA ... :-) haha > details, as said, PLL and DLL...Another interesting question I read from a newspaper yesterday, how to get more than 10% gain if share prices increase by 10%?
Reply by ●February 22, 20082008-02-22
Clemens Blank <CBlank@hotmail.com> wrote:>Hi > >I just came across some interview questions for digital design, and >would like to discuss my solutions with you! > >#Design a circuit to divide input frequency by 2 >I could do this with a Toggle Flip flop where the inverted output >is connected to the input, then i also divide the clock frequency by two > ># Design a divide-by-3/divide-by-5 sequential circuit with 50% duty cycle. >I was thinking of having here a statemachine that outputs for 3 cycles >0, and then it changes the state to output 3 times a 1 at each clock >transition. > ># Which one is superior: Asynchronous Reset or Synchronous Reset > >Well, until now I was always using asynchronous resets because u >find it in most textbooks ;) not so sure about the right answer here!The best answer to all these questions is a question. Starting with the architecture / type of logic. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)
