Xilinx DCM for frequency synthesis -- newbie question

I'm trying to use a DCM on a Spartan 3E to synthesize a frequency
of 8 MHz but see only a constant 2 volts on the CLKFX output.  The
google hits on this did not help.

It must be a simple mistake; any ideas what I'm doing wrong?
The "****" indicate the lines from the prototype that I've changed.

thanks
Bob Smith


==================================================================================
module clocks(clkin, clkout1, clkout2);

input clkin;     // Digilent Spartan 3e starter kit 50 MHz clock
output clkout1;  // Wanna be 8 MHz
output clkout2;  // 50 MHz/32 for comparison

reg [7:0] count;

always @(posedge clkin)
begin
     count <= count + 1;
end

assign clkout2 = count[4];


DCM #(
       .CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
                           //   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
       .CLKFX_DIVIDE(25),   // Can be any integer from 1 to 32       **************
       .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32        ************
       .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
       .CLKIN_PERIOD(20.0),  // Specify period of input clock        ***********
       .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
       .CLK_FEEDBACK("NONE"),  // Specify clock feedback of NONE, 1X or 2X  *********
       .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
                                             //   an integer from 0 to 15
       .DFS_FREQUENCY_MODE("LOW"),  // HIGH or LOW frequency mode for frequency synthesis
       .DLL_FREQUENCY_MODE("LOW"),  // HIGH or LOW frequency mode for DLL
       .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
       .FACTORY_JF(16'hC080),   // FACTORY JF values
       .PHASE_SHIFT(0),     // Amount of fixed phase shift from -255 to 255
       .STARTUP_WAIT("FALSE")   // Delay configuration DONE until DCM LOCK, TRUE/FALSE
    ) DCM_inst (
       .CLK0(CLK0),     // 0 degree DCM CLK output
       .CLK180(CLK180), // 180 degree DCM CLK output
       .CLK270(CLK270), // 270 degree DCM CLK output
       .CLK2X(CLK2X),   // 2X DCM CLK output
       .CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
       .CLK90(CLK90),   // 90 degree DCM CLK output
       .CLKDV(CLKDV),   // Divided DCM CLK out (CLKDV_DIVIDE)
       .CLKFX(clkout1),   // DCM CLK synthesis out (M/D)          ************
       .CLKFX180(CLKFX180), // 180 degree CLK synthesis out
       .LOCKED(LOCKED), // DCM LOCK status output
       .PSDONE(PSDONE), // Dynamic phase adjust done output
       .STATUS(STATUS), // 8-bit DCM status bits output
       .CLKFB(CLKFB),   // DCM clock feedback
       .CLKIN(clkin),   // Clock input (from IBUFG, BUFG or DCM)   ************
       .PSCLK(PSCLK),   // Dynamic phase adjust clock input
       .PSEN(PSEN),     // Dynamic phase adjust enable input
       .PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
       .RST(RST)        // DCM asynchronous reset input
);

endmodule

On Feb 23, 3:06 am, Bob Smith <use...@linuxtoys.org> wrote:
> I'm trying to use a DCM on a Spartan 3E to synthesize a frequency
> of 8 MHz but see only a constant 2 volts on the CLKFX output.  The
> google hits on this did not help.
>
> It must be a simple mistake; any ideas what I'm doing wrong?
> The "****" indicate the lines from the prototype that I've changed.
>
> thanks
> Bob Smith
>
> ==================================================================================
> module clocks(clkin, clkout1, clkout2);
>
> input clkin;     // Digilent Spartan 3e starter kit 50 MHz clock
> output clkout1;  // Wanna be 8 MHz
> output clkout2;  // 50 MHz/32 for comparison
>
> reg [7:0] count;
>
> always @(posedge clkin)
> begin
>      count <= count + 1;
> end
>
> assign clkout2 = count[4];
>
> DCM #(
>        .CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
>                            //   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
>        .CLKFX_DIVIDE(25),   // Can be any integer from 1 to 32       **************
>        .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32        ************
>        .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
>        .CLKIN_PERIOD(20.0),  // Specify period of input clock        ***********
>        .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
>        .CLK_FEEDBACK("NONE"),  // Specify clock feedback of NONE, 1X or 2X  *********
>        .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
>                                              //   an integer from 0 to 15
>        .DFS_FREQUENCY_MODE("LOW"),  // HIGH or LOW frequency mode for frequency synthesis
>        .DLL_FREQUENCY_MODE("LOW"),  // HIGH or LOW frequency mode for DLL
>        .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
>        .FACTORY_JF(16'hC080),   // FACTORY JF values
>        .PHASE_SHIFT(0),     // Amount of fixed phase shift from -255 to 255
>        .STARTUP_WAIT("FALSE")   // Delay configuration DONE until DCM LOCK, TRUE/FALSE
>     ) DCM_inst (
>        .CLK0(CLK0),     // 0 degree DCM CLK output
>        .CLK180(CLK180), // 180 degree DCM CLK output
>        .CLK270(CLK270), // 270 degree DCM CLK output
>        .CLK2X(CLK2X),   // 2X DCM CLK output
>        .CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
>        .CLK90(CLK90),   // 90 degree DCM CLK output
>        .CLKDV(CLKDV),   // Divided DCM CLK out (CLKDV_DIVIDE)
>        .CLKFX(clkout1),   // DCM CLK synthesis out (M/D)          ************
>        .CLKFX180(CLKFX180), // 180 degree CLK synthesis out
>        .LOCKED(LOCKED), // DCM LOCK status output
>        .PSDONE(PSDONE), // Dynamic phase adjust done output
>        .STATUS(STATUS), // 8-bit DCM status bits output
>        .CLKFB(CLKFB),   // DCM clock feedback
>        .CLKIN(clkin),   // Clock input (from IBUFG, BUFG or DCM)   ************
>        .PSCLK(PSCLK),   // Dynamic phase adjust clock input
>        .PSEN(PSEN),     // Dynamic phase adjust enable input
>        .PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
>        .RST(RST)        // DCM asynchronous reset input
> );
>
> endmodule

I know this sounds like a simple answer, but have you checked your
input clock? That was an issue I just had recently. My external
oscillator was not generating its 100MHz signal.

-- Mike

morphiend wrote:
> On Feb 23, 3:06 am, Bob Smith <use...@linuxtoys.org> wrote:
>> I'm trying to use a DCM on a Spartan 3E to synthesize a frequency
>> of 8 MHz but see only a constant 2 volts on the CLKFX output.  The
>> google hits on this did not help.
>>
>> It must be a simple mistake; any ideas what I'm doing wrong?
>> The "****" indicate the lines from the prototype that I've changed.


>> always @(posedge clkin)
>> begin
>>      count <= count + 1;
>> end
>>
>> assign clkout2 = count[4];

> I know this sounds like a simple answer, but have you checked your
> input clock? That was an issue I just had recently. My external
> oscillator was not generating its 100MHz signal.

Mike
     Thanks for the suggestion.  Yeah, the divide by 32 was a way
to prove that the clock is there.  The code (now snipped) builds
and seems to run fine but there's no output on CLKFX.

thanks
Bob

>>> assign clkout2 = count[4];
> 
>> I know this sounds like a simple answer, but have you checked your
>> input clock? That was an issue I just had recently. My external
>> oscillator was not generating its 100MHz signal.
> 
> Mike
>     Thanks for the suggestion.  Yeah, the divide by 32 was a way
> to prove that the clock is there.  The code (now snipped) builds
> and seems to run fine but there's no output on CLKFX.
> 
> thanks
> Bob

  Have you checked the locked output? if it's not locked, FX would not
output anything iirc, as opposed to clk0 which does regardless of lock.

-P@

On Feb 23, 1:06 pm, Bob Smith <use...@linuxtoys.org> wrote:
> I'm trying to use a DCM on a Spartan 3E to synthesize a frequency
> of 8 MHz but see only a constant 2 volts on the CLKFX output.  The
> google hits on this did not help.


your DCM is missing reset, if I am not wrong.
I dont see any reset on your top level port list.
You are getting clkout2, because it is not depending on reset.

Please check.

Regards,
JK

JK wrote:
> your DCM is missing reset, if I am not wrong.
> I dont see any reset on your top level port list.
> You are getting clkout2, because it is not depending on reset.

Thanks for the suggestion.  I added a reset from a switch on the
board.  A reset does not seem to make any difference.


PatC wrote:
 >   Have you checked the locked output? if it's not locked, FX would not
 > output anything iirc, as opposed to clk0 which does regardless of lock.

Thanks for the suggestion.  I tied an LED on the board to the
locked status output.  The locked status never goes high (perhaps
as you suspected).   Any ideas why it won't lock?


JK and PatC, thanks both.

Bob Smith

> PatC wrote:
>
>  >   Have you checked the locked output? if it's not locked, FX would not
>  > output anything iirc, as opposed to clk0 which does regardless of lock.
>
> Thanks for the suggestion.  I tied an LED on the board to the
> locked status output.  The locked status never goes high (perhaps
> as you suspected).   Any ideas why it won't lock?
>
> JK and PatC, thanks both.
>
> Bob Smith

See the line
.CLK_FEEDBACK("NONE"),  // Specify clock feedback of NONE, 1X or 2X
*********

The DLL needs clock feedback to lock (and work). So try setting this
to 1X.

mng wrote:
>>  >   Have you checked the locked output? if it's not locked, FX would not
>>  > output anything iirc, as opposed to clk0 which does regardless of lock.

> 
> See the line
> .CLK_FEEDBACK("NONE"),  // Specify clock feedback of NONE, 1X or 2X
> *********
> 
> The DLL needs clock feedback to lock (and work). So try setting this
> to 1X.


Michael,
   Thanks for the suggestion.  Changing the feedback to 1X did not make
a difference although it builds fine.   I could have sworn that using
1X in an earlier attempt gave me an error saying that frequency synthesis
needed NONE.  The Spartan 3 Users Guide (pg 70) says kind of the same
thing.

thanks
Bob Smith

Bob Smith wrote:
> JK wrote:
>> your DCM is missing reset, if I am not wrong.
>> I dont see any reset on your top level port list.
>> You are getting clkout2, because it is not depending on reset.
> 
> Thanks for the suggestion.  I added a reset from a switch on the
> board.  A reset does not seem to make any difference.
> 
> 
> PatC wrote:
>>   Have you checked the locked output? if it's not locked, FX would not
>> output anything iirc, as opposed to clk0 which does regardless of lock.
> 
> Thanks for the suggestion.  I tied an LED on the board to the
> locked status output.  The locked status never goes high (perhaps
> as you suspected).   Any ideas why it won't lock?

Since your code sample is snipped, I don't see the BUFG connecting clk0
to clkfb. If you are using clock feedback 1x, this is how it should be
connected. Without this feedback, it won't lock.

-P@

On Feb 24, 8:53 pm, PatC <p...@patocarr.com> wrote:
> Bob Smith wrote:
> > JK wrote:
> >> your DCM is missing reset, if I am not wrong.
> >> I dont see any reset on your top level port list.
> >> You are getting clkout2, because it is not depending on reset.
>
> > Thanks for the suggestion.  I added a reset from a switch on the
> > board.  A reset does not seem to make any difference.
>
> > PatC wrote:
> >>   Have you checked the locked output? if it's not locked, FX would not
> >> output anything iirc, as opposed to clk0 which does regardless of lock.
>
> > Thanks for the suggestion.  I tied an LED on the board to the
> > locked status output.  The locked status never goes high (perhaps
> > as you suspected).   Any ideas why it won't lock?
>
> Since your code sample is snipped, I don't see the BUFG connecting clk0
> to clkfb. If you are using clock feedback 1x, this is how it should be
> connected. Without this feedback, it won't lock.
>
> -P@

When using the DCM for frequency synthesis only you are correct in
saying that you don't need to feedback a signal and setting
CLK_FEEDBACK to NONE is the right thing to do. I've succesfully used
this configuration myself.
Strange that the output is at 2V, is this the IO voltage for that
bank? If you haven't already done so, i suggest you try and simulate
the design, as this may give some clue as to what is going on.
Without a RST input you also need to be careful that the clock is
running and stable before configuration. Any change in the input clock
requires RST to be asserted.
I'm also not sure that the LOCKED pin should go high, since the
datasheet states that this is asserted when CLKIN and CLKFB are in
phase, which of course will never happen in this configuration.

Cheers
Rob