clock distribution accross boards

Hi,

maybe you folks can help me with a design decision:

I need to distribute a clock to up to ten identical boards.
The boards are all plugged into a backplane in a single row.

In addition to the backplane the boards will be connected by
a twinax flatband cable on samtec connectors. For the clock
distribution I can choose between a bus structure cable or a
series of point to point connections between neighbouring boards.

The leftmost of the identical boards shall provide a clock for all
the other boards. I am now concerned that a bus structure with
that many stubs will have problems maintaining a good signal quality.

I could instead use point to point connections with fanout clock
buffers on each board to forward the clock to the next board. As far
as the signal quality goes this will obviously work very well,
BUT the boards need a fixed phase relationship. While the absolute
phase is of no importance, the phase must not drift over time or
temperature by more than 50ps or so. Ten buffers in a row would
probably have a larger drift, wouldn't they?

Any ideas, how I can make a pure passive distribution work in a setup
like that?

Also: How can I turn on the termination on the last board dynamically?


Kolja Sulimma

On Mar 3, 8:27=A0am, Kolja Sulimma <ksuli...@googlemail.com> wrote:
> Hi,
>
> maybe you folks can help me with a design decision:
>
> I need to distribute a clock to up to ten identical boards.
> The boards are all plugged into a backplane in a single row.
>
> In addition to the backplane the boards will be connected by
> a twinax flatband cable on samtec connectors. For the clock
> distribution I can choose between a bus structure cable or a
> series of point to point connections between neighbouring boards.
>
> The leftmost of the identical boards shall provide a clock for all
> the other boards. I am now concerned that a bus structure with
> that many stubs will have problems maintaining a good signal quality.
>
> I could instead use point to point connections with fanout clock
> buffers on each board to forward the clock to the next board. As far
> as the signal quality goes this will obviously work very well,
> BUT the boards need a fixed phase relationship. While the absolute
> phase is of no importance, the phase must not drift over time or
> temperature by more than 50ps or so. Ten buffers in a row would
> probably have a larger drift, wouldn't they?
>
> Any ideas, how I can make a pure passive distribution work in a setup
> like that?
>
> Also: How can I turn on the termination on the last board dynamically?
>
> Kolja Sulimma

I would generate the clock on the center board, then fan out in both
directions and terminate on both ends, which of course means that the
driver sees half the characteristic impedance...
Peter Alfke

On Mar 3, 8:27=A0am, Kolja Sulimma <ksuli...@googlemail.com> wrote:
> Hi,
>
> maybe you folks can help me with a design decision:
>
> I need to distribute a clock to up to ten identical boards.
> The boards are all plugged into a backplane in a single row.
>
> In addition to the backplane the boards will be connected by
> a twinax flatband cable on samtec connectors. For the clock
> distribution I can choose between a bus structure cable or a
> series of point to point connections between neighbouring boards.
>
> The leftmost of the identical boards shall provide a clock for all
> the other boards. I am now concerned that a bus structure with
> that many stubs will have problems maintaining a good signal quality.
>
> I could instead use point to point connections with fanout clock
> buffers on each board to forward the clock to the next board. As far
> as the signal quality goes this will obviously work very well,
> BUT the boards need a fixed phase relationship. While the absolute
> phase is of no importance, the phase must not drift over time or
> temperature by more than 50ps or so. Ten buffers in a row would
> probably have a larger drift, wouldn't they?
>
> Any ideas, how I can make a pure passive distribution work in a setup
> like that?
>
> Also: How can I turn on the termination on the last board dynamically?
>
> Kolja Sulimma

Kolja,

Have you considered using a clock buffer on the backplane?  By using
point-to-point connections, your design is significantly cleaner but
you no longer have a passive-only backplane solution.

- John_H

Kolja Sulimma wrote:
> Hi,
>
> maybe you folks can help me with a design decision:
>
> I need to distribute a clock to up to ten identical boards.
> The boards are all plugged into a backplane in a single row.
>
>
> The leftmost of the identical boards shall provide a clock for all
> the other boards. I am now concerned that a bus structure with
> that many stubs will have problems maintaining a good signal quality.
>
Hi Kolja,

Thinking as I type...

1) What frequency is the clock? The higher the frequency, the more likely 
you are to have problems with reflections from an edge during the next edge.
2) What is the rise time of the clock? The faster the rise time, the bigger 
the reflections, in general.
3) What logic standard is the clock?
4) What does the clock drive on the destination cards? FPGAs have relatively 
large pin capacitance which can cause big reflections at fast edge rates.

Your 50ps requirement rules out any tricks with DCMs, they have that much 
phase noise and more already.

I like your daisy chain plan. As you are worried about 50ps, this must be 
the safest way to go. You could use something like the SY58011u 1:2 CML 
buffer from Micrel, depending on your operating temperature range. The 
datasheet has a graph of propagation delay versus temperature. From 10C to 
80C the delay changes by 10ps more or less linearly. If you can keep the 
temperature range low, this might be ok. Use one output to drive the board, 
the other to drive the next board. They also make 1:4 parts, so the first 
board could drive the next 3, the 4th drives 5,6,7 and so on. So you'd have 
fewer buffers.

Oh, yeah. Simulate it!

HTH., Syms. 

Kolja,

I hate to say it, but why do you wish to architect a system that has
this requirement?  Why not solve the problem in a way that does not
require this 50ps phase alignment?  The added FIFO buffering may be well
worth the pain of precise clock phase control/signal integrity.

My two pennies,

Austin

Kolja,

You could distribute some slow clock and generate your fast clocks on each 
board independently with high quality PLLs but that's not a pure passive 
solution you've asked for...

/Mikhail

That is a simple question:
It is a device to measure the timing of input signals. We have 25ps
resolution now and want to improve on that.
The problem ist that we can only fit 8 inputs on any board. Most
customers need only less than 8 channels, but some
need a lot more. These are important customers, but the volume is
really low, so we would rather use a standard backplane
with our standard boards.

Kolja


On 3 Mrz., 19:43, austin <aus...@xilinx.com> wrote:
> Kolja,
>
> I hate to say it, but why do you wish to architect a system that has
> this requirement?  Why not solve the problem in a way that does not
> require this 50ps phase alignment?  The added FIFO buffering may be well
> worth the pain of precise clock phase control/signal integrity.
>
> My two pennies,
>
> Austin

That is OK. We definitely will have jitter cleanup PLLs on the boards.
I am not looking for a passive solution because I want a simple or
cheap solution,
but because I am worried by the temperature dependant delay of the
active components.

Kolja

On 3 Mrz., 22:54, "MM" <mb...@yahoo.com> wrote:
> Kolja,
>
> You could distribute some slow clock and generate your fast clocks on each
> board independently with high quality PLLs but that's not a pure passive
> solution you've asked for...
>
> /Mikhail

On 3 Mrz., 18:45, "Symon" <symon_bre...@hotmail.com> wrote:
> 1) What frequency is the clock? The higher the frequency, the more likely
> you are to have problems with reflections from an edge during the next edg=
e.

And otherwise you think I can get a clean  enough edge across 10
stubs?
(or 5 using Peters suggestion).
The setup is rather complex for a simulation.

> 2) What is the rise time of the clock? The faster the rise time, the bigge=
r
> the reflections, in general.
Well, fast risetimes is a way to reduce phase shifts due to variations
in threshold
and supply voltage. So currently I am looking into very fast rise
times.

> 3) What logic standard is the clock?
Free to choose. I am looking at CML and LVDS currently.

> 4) What does the clock drive on the destination cards? FPGAs have relative=
ly
> large pin capacitance which can cause big reflections at fast edge rates.
Good point, I did not think of that. Maybe external clock buffers on
the inputs
could improve on that.

> Your 50ps requirement rules out any tricks with DCMs, they have that much
> phase noise and more already.
Even external zero delay buffers often have something like 200ps skew.

> I like your daisy chain plan. As you are worried about 50ps, this must be
> the safest way to go. You could use something like the SY58011u 1:2 CML
> buffer from Micrel, depending on your operating temperature range. The
> datasheet has a graph of propagation delay versus temperature. From 10C to=

> 80C the delay changes by 10ps more or less linearly. If you can keep the
> temperature range low, this might be ok. Use one output to drive the board=
,
> the other to drive the next board. They also make 1:4 parts, so the first
> board could drive the next 3, the 4th drives 5,6,7 and so on. So you'd hav=
e
> fewer buffers.
That is a great suggestion. I had a look at multiple parts but only
one of those
specified the temperature effect - which was to big. 10ps over 70=B0C is
rather good.
The linear solution has the advantage that it is easy to make all
boards identical.

> Oh, yeah. Simulate it!

*sigh* It's a big task for simulation. But I probably will have to.

On 3 Mrz., 18:23, John_H <newsgr...@johnhandwork.com> wrote:
> On Mar 3, 8:27 am, Kolja Sulimma <ksuli...@googlemail.com> wrote:
>
>
>
> > Hi,
>
> > maybe you folks can help me with a design decision:
>
> > I need to distribute a clock to up to ten identical boards.
> > The boards are all plugged into a backplane in a single row.
>
> > In addition to the backplane the boards will be connected by
> > a twinax flatband cable on samtec connectors. For the clock
> > distribution I can choose between a bus structure cable or a
> > series of point to point connections between neighbouring boards.
>
> > The leftmost of the identical boards shall provide a clock for all
> > the other boards. I am now concerned that a bus structure with
> > that many stubs will have problems maintaining a good signal quality.
>
> > I could instead use point to point connections with fanout clock
> > buffers on each board to forward the clock to the next board. As far
> > as the signal quality goes this will obviously work very well,
> > BUT the boards need a fixed phase relationship. While the absolute
> > phase is of no importance, the phase must not drift over time or
> > temperature by more than 50ps or so. Ten buffers in a row would
> > probably have a larger drift, wouldn't they?
>
> > Any ideas, how I can make a pure passive distribution work in a setup
> > like that?
>
> > Also: How can I turn on the termination on the last board dynamically?
>
> > Kolja Sulimma
>
> Kolja,
>
> Have you considered using a clock buffer on the backplane?  By using
> point-to-point connections, your design is significantly cleaner but
> you no longer have a passive-only backplane solution.
>
> - John_H

That would work, but than we need custom made backplanes.
An intermediate solution is to have one special board that provides
ten clock lines
and then shifting the clock lines by one on each board. Of course this
clogges 20 lines
on the cable.

Kolja Sulimma