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Cyclone III and Quartus 7.2sp2

Started by sdf March 8, 2008
Hi.
Analysis and Synthesis for Cyclone III is SO slow.. One my design with
about 30000 ALUTs was analysed and synthesed more than 12 hours and I
finally breaked it. Target device was set to EP3C25F324 (from Cyclone
III FPGA Starter Kit).
The same design analysed and synthesed for Stratix II EP2S60 less than
for one hour. My computer is Intel Core Duo 2.40GHz and 2Gb of RAM.
Is this OK? Am I forgot to turn on/off something in Quartus?
I wonder if it has anything to do with the fact that the EP3C25 only has 
24,624 logic elements and you claim your design uses 30,000.  The EP2S60 
has 60,000 logic elements

sdf wrote:
> Hi. > Analysis and Synthesis for Cyclone III is SO slow.. One my design with > about 30000 ALUTs was analysed and synthesed more than 12 hours and I > finally breaked it. Target device was set to EP3C25F324 (from Cyclone > III FPGA Starter Kit). > The same design analysed and synthesed for Stratix II EP2S60 less than > for one hour. My computer is Intel Core Duo 2.40GHz and 2Gb of RAM. > Is this OK? Am I forgot to turn on/off something in Quartus?
On Mar 8, 4:40=A0pm, Rob <buz...@leavemealone.com> wrote:
> I wonder if it has anything to do with the fact that the EP3C25 only has > 24,624 logic elements and you claim your design uses 30,000. =A0The EP2S60=
> has 60,000 logic elements
Sorry, it's my mistake in post. I divided my design, so it should fin in 7 or 8 thousands ALUTs. That was the case when Quartus worked more than 12 hours and I breaked it.
sdf wrote:

> Analysis and Synthesis for Cyclone III is SO slow.. One my design with > about 30000 ALUTs was analysed and synthesed more than 12 hours and I > finally breaked it. Target device was set to EP3C25F324
Set quartus to the EP3C family and let it pick the device. -- Mike Treseler
sdf wrote:

> Analysis and Synthesis for Cyclone III is SO slow.. One my design with > about 30000 ALUTs was analysed and synthesed more than 12 hours and I > finally breaked it. Target device was set to EP3C25F324 (from Cyclone > III FPGA Starter Kit). > The same design analysed and synthesed for Stratix II EP2S60 less than > for one hour. My computer is Intel Core Duo 2.40GHz and 2Gb of RAM. > Is this OK? Am I forgot to turn on/off something in Quartus?
If your design is highly interconnected, the fitter may not be able to place and route it. But with 8 thousand ALUTs it might tell you this only after lots of hours trying. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.de
On Mar 8, 6:18 am, sdf <drop...@gmail.com> wrote:
> Hi. > Analysis and Synthesis for Cyclone III is SO slow.. One my design with > about 30000 ALUTs was analysed and synthesed more than 12 hours and I > finally breaked it. Target device was set to EP3C25F324 (from Cyclone > III FPGA Starter Kit). > The same design analysed and synthesed for Stratix II EP2S60 less than > for one hour. My computer is Intel Core Duo 2.40GHz and 2Gb of RAM. > Is this OK? Am I forgot to turn on/off something in Quartus?
Cyclones (I, II, III) doesn't use ALUT, but regular LUTs. Altera estimates an ALUT to be equivalent to 2.5 LUTs, thus you're asking for 75,000 LUTs in a 24,624 LUT device. Assuming this is not just a trivial typo, it's totally expected to take a long time to synthesize when the device is full. As a general rule however, turning off all the advanced synthesize and fitter options will speed up the process. Also, aggressive timing constraints will force both to work harder. Tommy
On Mar 9, 1:03=A0am, Tommy Thorn <tommy.th...@gmail.com> wrote:

> Cyclones (I, II, III) doesn't use ALUT, but regular LUTs. Altera > estimates > an ALUT to be equivalent to 2.5 LUTs, thus you're asking for 75,000 > LUTs > in a 24,624 LUT device. Assuming this is not just a trivial typo, it's > totally > expected to take a long time to synthesize when the device is full.
Ah, now I understand the difference between Cyclone and Stratix. Thank you for your reply.
On Mar 8, 6:53 pm, sdf <drop...@gmail.com> wrote:
> On Mar 9, 1:03 am, Tommy Thorn <tommy.th...@gmail.com> wrote: > > > Cyclones (I, II, III) doesn't use ALUT, but regular LUTs. Altera > > estimates > > an ALUT to be equivalent to 2.5 LUTs, thus you're asking for 75,000 > > LUTs > > in a 24,624 LUT device. Assuming this is not just a trivial typo, it's > > totally > > expected to take a long time to synthesize when the device is full. > > Ah, now I understand the difference between Cyclone and Stratix. > Thank you for your reply.
Not quite! Only Stratix II, III, GX II, and Arria GX uses the new structure. (BTW, they are called ALM, whereas the "old" cells were LE). Off-topic: ALM are IMO the most interesting thing that has happened in the FPGA world in years, but I haven't had opportunity to use them yet. Functionally Virtex 5's LUT6 are a strict subset of the ALM (modulo the SRL32 part), but on paper, the ALM is much more powerful and flexible. In the real world everything depends on what the design software does with them. Tommy
On Mar 9, 6:51=A0pm, Tommy Thorn <tommy.th...@gmail.com> wrote:
> Off-topic: > ALM are IMO the most interesting thing that has happened in the FPGA > world in years, but I haven't had opportunity to use them yet. > Functionally > Virtex 5's LUT6 are a strict subset of the ALM (modulo the SRL32 > part), > but on paper, the ALM is much more powerful and flexible. In the real > world everything depends on what the design software does with them.
Another question is, when it will be possible to program FPGA at low- level, without synthesis and fitting, just like low-level coders downgrading to x86 assembler in past.. I believe, there're some people who eventually wish to try this, if it will be possible.
Tommy wrote:

>> Virtex 5's LUT6 are a strict subset of the ALM (modulo the SRL32 >> part), >> but on paper, the ALM is much more powerful and flexible. In the real >> world everything depends on what the design software does with them.
Quartus seems to use them rationally. sdf wrote:
> Another question is, when it will be possible to program FPGA at low- > level, without synthesis and fitting, just like low-level coders > downgrading to x86 assembler in past..
Long past, and the analogy is weak since assembly language was once standard practice and it is still supported with tools. I suppose I could make a netlist of LUTs and flops instead of vhdl synthesis, but I see no way to do manual place+route or static timing for fpgas.
> I believe, there're some people who eventually wish to try this, if it > will be possible.
I've never met such a person. -- Mike Treseler