its regarding to the Max Frequency in xilinx FPGA

Hi,
to all i am new to this group which a great place to share and find
the more discussions environment.

so my question is on xilinx virtex series FPGA's

1. every virtex series is having maximum frequency where we can use in
some of higher end applications,so virtex, virtexII, virtex-E, and
virtex-II Pro all serieses are having their Max frequency based on
upgradations. So xilinx will design on what kind of basis to enhance
the frequency in higer versions of these serieses and is that every
logic( wether they are combinational or sequential type) having same
kind of frequency(what Max frequency of FPGA is having).?

May this question in easier one,...but if any one having a good
answer...it will be a great thing.

regards,
Sreeni,
Moog,Inc

On Mar 10, 5:22 am, jshrini.v...@gmail.com wrote:
> Hi,
> to all i am new to this group which a great place to share and find
> the more discussions environment.
>
> so my question is on xilinx virtex series FPGA's
>
> 1. every virtex series is having maximum frequency where we can use in
> some of higher end applications,so virtex, virtexII, virtex-E, and
> virtex-II Pro all serieses are having their Max frequency based on
> upgradations. So xilinx will design on what kind of basis to enhance
> the frequency in higer versions of these serieses and is that every
> logic( wether they are combinational or sequential type) having same
> kind of frequency(what Max frequency of FPGA is having).?
>
> May this question in easier one,...but if any one having a good
> answer...it will be a great thing.
>
> regards,
> Sreeni,
> Moog,Inc

Speed enhancements in newer generation FPGA's come from 2 sources.
The first is process enhancements (usually reduced geometry) which
is something developed mostly by the fabrication partner and to
some extent "tweaked" by Xilinx.  Reduced geometry generally
results in better speed as well as increased density.

The second is architecture enhancements.  These have additional
impact on device speed that can be carried over to further
process generations.  The original Virtex series gained a
great deal of speed in its routing for example over the
previous generations of Xilinx FPGA which had passive routing
connections.  Virtex 5 has increased the LUT size to 6-inputs
which can reduce logic levels in complex designs.

Process enhancements generally affect all of the chip timing
parameters, while architecture enhancements can affect only
some timing parameters, or some more than others.  For example
increasing the LUT size doesn't generally affect the maximum
toggle rate of the fabric flip-flops.  Depending on what you
do with the FPGA some architecture enhancements can make
a tremendous difference in performance, for example the
addition of DSP48 for signal-processing applications.  These
same enhancements may make no difference at all to other
designs that implement a lot of random state-machines.

I'm sure Austin can point out a number of other improvements
over time in the Virtex series, as well as a sense of where
more speed enhancements may come from in future generations.

Regards,
Gabor

"Gabor" <gabor@alacron.com> wrote in message 
news:ef6b6505-5146-450f-b6cf-b66c5f0cc70e@59g2000hsb.googlegroups.com...
> Speed enhancements in newer generation FPGA's come from 2 sources.
> The first is process enhancements (usually reduced geometry) which
> is something developed mostly by the fabrication partner and to
> some extent "tweaked" by Xilinx.  Reduced geometry generally
> results in better speed as well as increased density.
>

It is also possible to get process-enhancement driven performance increase 
without any physical design changes, such as geometry shrinks. When a vendor 
offers multiple speed-grades of the same part, as Xilinx do, all the parts 
are built the same and then sorted at test. As one gets better at making the 
parts it can be the case that enough are faster than the fastest part 
marketed to introduce a new faster version. This used to be a big thing a 
few years ago, but I suspect these days the variation is less because of 
tighter control over processes from the outset.

Don't forget progress in characterization.

Often you do not know exactly how fast all the pathes in your design
are over all operating conditions.
IBM stated up to 30% deviation from SPICE simulation to measured chip
in some cases at the ISPD2001 conference.
This is especially  true for SOI circuits were switching speed depends
on the signal history.

Within the lifetime of a product the understanding of the device
timing improves and tighter values can be published.
Therefore you sometimes can sometimes improve the guaranteed
performance of a design just by downloading a new
speedfile.

Also: Depending on your design style software improvements in the
design tools can have a positive effect on timing.

Kolja Sulimma

On Mar 10, 5:22 am, jshrini.v...@gmail.com wrote:
> 1. every virtex series is having maximum frequency where we can use in
> some of higher end applications,so virtex, virtexII, virtex-E, and
> virtex-II Pro all serieses are having their Max frequency based on
> upgradations. So xilinx will design on what kind of basis to enhance
> the frequency in higer versions of these serieses and is that every
> logic( wether they are combinational or sequential type) having same
> kind of frequency(what Max frequency of FPGA is having).?

Howdy Sreeni,

BTW, not everything gets faster in newer generations.  That may have
been true through V2Pro, but when we took our pipelined 311 MHz design
to V4 certain things did get slower - I believe one of the biggest was
related to LUT-RAM's.  Going from V4 to V5, we took another F-max hit,
this time related to a huge (bad) change in timing for the mode that
we are running the BRAM's in (the original design didn't have
registered outputs, and it would be a big deal to change it), and
surprisingly, routing. We have 3.1 ns to work with, and we have way
too many routes that are 2.5 to 3.5 ns.  Part of this could likely be
fixed with improvement to the tools - one path I was inspecting last
night looked like register duplication would fix it - yet the tools
weren't inserting duplicate registers.

Lastly, also related to tools: they seem to do better if you don't
give them a grossly over-large part to work with.  Pick a part close
to the size you need (in terms of LUTs).

   Marc