In most FPGA designs I've done there's been an external reset input which has been used as the power on reset mechanism. I'm now doing a design for a Spartan-3 with no external reset, and I've some signals I need pre-set so I need to use the internal asynch reset mechanism. I've read here in the past of the problems of using the GSR, but in this design there are synchronous enables which control the data flow. The functionality of these means there shouldn't be any timing problems out of reset. I was under the impression that if you had a top level signal which was used in the usual VHDL asynchronous reset template manner, the synthesis tools would pick it out and connect it to the GSR net. I'm using XST and getting .. "Signal <rst> is used but never assigned. Tied to value 0." So what do I need to do to get 'rst' connected to the GSR net? I've spent a fair bit of time searching the Xilinx site/docs and googling this group with no results. It seems to be one of those things that I should probably know, but just can't find anywhere. Thanks for any pointers, Nial.
GSR in Spartan3 ?
Started by ●February 16, 2004
Reply by ●February 16, 20042004-02-16
> So what do I need to do to get 'rst' connected to the GSR > net? > > I've spent a fair bit of time searching the Xilinx site/docs > and googling this group with no results. It seems to be one > of those things that I should probably know, but just can't > find anywhere. > > Thanks for any pointers, > > Nial. >Hi Nial, Can you instantiate the STARTBUF_SPARTAN3 design element? Listed under STARTBUF_architecture in the Design Elements section of the Libraries guide. Cheers mate, Syms. p.s. I see Mr.Easton's expecting again! There should be a law against it!
Reply by ●February 17, 20042004-02-17
"Symon" <symon_brewer@hotmail.com> wrote in message news:c0rrgi$1b7t8e$1@ID-212844.news.uni-berlin.de...> > > So what do I need to do to get 'rst' connected to the GSR > > net? > > > > I've spent a fair bit of time searching the Xilinx site/docs > > and googling this group with no results. It seems to be one > > of those things that I should probably know, but just can't > > find anywhere. > > > > Thanks for any pointers, > > > > Nial. > > > Hi Nial, > Can you instantiate the STARTBUF_SPARTAN3 design element? Listed under > STARTBUF_architecture in the Design Elements section of the Librariesguide.> Cheers mate, Syms.Symon, that doesn't do it. The STARTUP_SPARTAN3 module allows you to drive the GSR net from an user defined source but this reset mechanism isn't visible to HDL so simulations won't work. The STARTBUF_SPARTAN3 module does the same thing, but with an output you can connect to your HDL reset lines which mirrors the GSR net. Thus simulations should match real life. This doesn't help me tie my top level 'rst' net to the GSR. I've checked through my design and _all_ my asynch reset declarations use this net with the correct polarity. Any more ideas? Nial.
Reply by ●February 17, 20042004-02-17
There has been a push away from using GSR resources. Synthesisers probably now have the feature removed or turned off for modern families. I think this has been done mainly for simulation purposes and to speed up timing. My way around this is to use a small lfsr, or other counter, and recognise a pattern of '1's and '0's. Make your reset active when the pattern of the lfsr does not match you given final state (final state freezes count). Whatever default power up state of the flip-flops, be in '0' or '1', you won't start with pattern that releases reset. The output can be used for GSR driving or wired reset. John Adair Enterpoint Ltd. This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:40313fb8$0$6685$fa0fcedb@lovejoy.zen.co.uk...> In most FPGA designs I've done there's been an external reset > input which has been used as the power on reset mechanism. > > I'm now doing a design for a Spartan-3 with no external reset, > and I've some signals I need pre-set so I need to use the > internal asynch reset mechanism. > > I've read here in the past of the problems of using the GSR, > but in this design there are synchronous enables which > control the data flow. The functionality of these means there > shouldn't be any timing problems out of reset. > > I was under the impression that if you had a top level signal > which was used in the usual VHDL asynchronous reset template > manner, the synthesis tools would pick it out and connect it > to the GSR net. > > I'm using XST and getting .. > > "Signal <rst> is used but never assigned. Tied to value 0." > > > So what do I need to do to get 'rst' connected to the GSR > net? > > I've spent a fair bit of time searching the Xilinx site/docs > and googling this group with no results. It seems to be one > of those things that I should probably know, but just can't > find anywhere. > > Thanks for any pointers, > > > Nial. > >
Reply by ●February 17, 20042004-02-17
> There has been a push away from using GSR resources. Synthesisers probably > now have the feature removed or turned off for modern families. I thinkthis> has been done mainly for simulation purposes and to speed up timing.It looks like it John, a search for 'GSR' in the XST user guide only comes up with one hit, and that's for the Synplicity directive "xc_isgsr" which has no XST equivalent.> My way around this is to use a small lfsr, or other counter, and recognisea> pattern of '1's and '0's. Make your reset active when the pattern of the > lfsr does not match you given final state (final state freezes count). > Whatever default power up state of the flip-flops, be in '0' or '1', you > won't start with pattern that releases reset. The output can be used forGSR> driving or wired reset.I'd thought of this, but it felt like a bit of a bodge. I suppose it should be reliable as the data sheet stipulates that the registers power up to '0' unless otherwise specified. Have you had any problems with it? I'll give it a go and see how I get on. Thanks, Nial.
Reply by ●February 17, 20042004-02-17
I have not had any issues doing this. The synthesiser will usually pick a flop macro with '0' default but if it chooses a '1' default type you are covered by looking for pattern of mixed '0's and '1's. It is very unlikely that the pattern you choose will be the same as the synthesiser by way of the power up defaults. You can always double check and have a look using FPGA Editor or the equivalent. John Adair Enterpoint Ltd. This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:4031fad1$0$25865$fa0fcedb@lovejoy.zen.co.uk...> > There has been a push away from using GSR resources. Synthesisersprobably> > now have the feature removed or turned off for modern families. I think > this > > has been done mainly for simulation purposes and to speed up timing. > > It looks like it John, a search for 'GSR' in the XST user guide only comes > up with one hit, and that's for the Synplicity directive "xc_isgsr" which > has no XST equivalent. > > > > My way around this is to use a small lfsr, or other counter, andrecognise> a > > pattern of '1's and '0's. Make your reset active when the pattern ofthe> > lfsr does not match you given final state (final state freezes count). > > Whatever default power up state of the flip-flops, be in '0' or '1', you > > won't start with pattern that releases reset. The output can be used for > GSR > > driving or wired reset. > > I'd thought of this, but it felt like a bit of a bodge. > I suppose it should be reliable as the data sheet stipulates that > the registers power up to '0' unless otherwise specified. > > Have you had any problems with it? > > I'll give it a go and see how I get on. > > Thanks, > > > Nial. > >
Reply by ●February 17, 20042004-02-17
Hi Nial, I'm not quite sure if it solves your problem, but i currently use the ROC (ResetOnConfiguration) primitive to connect the reset signal to the GSR. You'll find more information about it in the Xilinx "Libraries Guide" (lib.pdf). Kind regards, Lars.
Reply by ●February 17, 20042004-02-17
"Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:<4031ec0e$0$19544$fa0fcedb@lovejoy.zen.co.uk>...> > The STARTBUF_SPARTAN3 module does the same thing, but with an > output you can connect to your HDL reset lines which mirrors > the GSR net. Thus simulations should match real life. > > > This doesn't help me tie my top level 'rst' net to the GSR. > I've checked through my design and _all_ my asynch reset > declarations use this net with the correct polarity. > > Any more ideas? > > > Nial.Hi Nial, Yeah, tricky one, what I've done in the past is use the STARTBUF_whatever instantiation, its output connected to rst, and its input tied to an 'unconnected on the PCB' or an unbonded IOB with the PULLUP turned on. This stops things being optimised away. I've used John's method too; it's just as bodgy as the IOB method but gets the job done! In fact I just looked at my latest masterpiece; I did the IOB thing above but left out the STARTBUF_ instantiation. All my FFs get set or reset on power up correctly, as if by magic! Cheers, Syms.
Reply by ●February 17, 20042004-02-17
"Lars Unger" <larsu@ida.ing.tu-bs.de> wrote in message news:Pine.LNX.4.50.0402171641240.23416-100000@tom.ida.ing.tu-bs.de...> Hi Nial, > > I'm not quite sure if it solves your problem, but i currently use > the ROC (ResetOnConfiguration) primitive to connect the reset > signal to the GSR. You'll find more information about it in the > Xilinx "Libraries Guide" (lib.pdf). > > Kind regards, > Lars.Thanks Lars, I've implemented the reset count as discussed with John earlier. This looks cleaner though so I'll try it tomorrow and report back results. Nial
Reply by ●February 18, 20042004-02-18
> Thanks Lars, I've implemented the reset count as discussed with > John earlier. This looks cleaner though so I'll try it tomorrow > and report back results.Hmm. I've tried using the ROC component as Lars suggested. The syntheis report doesn't give many clues as to what's going on, it says... "Generating a Black Box for component <ROC>" ... which might be expected, but rst or GSR aren't mentioned. The map report says ... The trimmed logic reported below is either: 1. part of a cycle 2. part of disabled logic 3. a side-effect of other trimmed logic The signal "roc_inst_1" is unused and has been removed. Optimized Block(s): TYPE BLOCK GND XST_GND VCC XST_VCC BUF roc_inst_1 BUF roc_inst_2 ...which might suggest that ROC has been replaced with something else (ie a connection to the GSR net) but it doesn't explicitly state this. Can anyone confirm that this means the ROC component has been removed and the rst net has been connected to GSR? If I can't get this confirmed I'll stick with the startup counter. Time for an experiment with a SpartanII I think. Nial.