Hi. It's probably not very good place for asking such, but there're should be at least those who knows starting points. We need to design our own CPU which can be very slow. It can execute each instruction, let's say, up to 50 cycles. We don't care about speed, and we are also don't care about memory size for microcode, but we're really care about CPU unit size. Where to read about CPU designing techniques, which are about shifting all possible to microcode from CPU unit? Extreme case will be probably Turing machine, but it's not practical. CPU registers and instructions in our case should be looks like ARM9 processor, maybe.
Designing CPU
Started by ●March 17, 2008
Reply by ●March 17, 20082008-03-17
climber.tim@gmail.com wrote:>Hi. >It's probably not very good place for asking such, but there're should >be at least those who knows starting points. >We need to design our own CPU which can be very slow. It can execute >each instruction, let's say, up to 50 cycles. We don't care about >speed, and we are also don't care about memory size for microcode, but >we're really care about CPU unit size. >Where to read about CPU designing techniques, which are about shifting >all possible to microcode from CPU unit? Extreme case will be probably >Turing machine, but it's not practical. CPU registers and instructions >in our case should be looks like ARM9 processor, maybe.A simple technique is to just implement the very basic instructions a cpu needs and then implement the rest as software functions. Instructions that you ought to have: Jump: Load instruction pointer from memory JumpSub: Push current instruction pointer on stack (stack++) Return: Load instruction pointer from stack (stack--) Move memory -> register Move register -> memory Compare register <=> register and jump if equal Increase/Decrease register Shift left/right Add register + register -> register This should give basic functionality for a performance penalty.
Reply by ●March 17, 20082008-03-17
On Mon, 17 Mar 2008 01:37:43 -0700 (PDT), climber.tim@gmail.com wrote:>Hi. >It's probably not very good place for asking such, but there're should >be at least those who knows starting points. >We need to design our own CPU which can be very slow. It can execute >each instruction, let's say, up to 50 cycles. We don't care about >speed, and we are also don't care about memory size for microcode, but >we're really care about CPU unit size. >Where to read about CPU designing techniques, which are about shifting >all possible to microcode from CPU unit? Extreme case will be probably >Turing machine, but it's not practical. CPU registers and instructions >in our case should be looks like ARM9 processor, maybe.Have you looked at the obvious published options such as Picoblaze? It's tiny. Anything that looks like an ARM9 will NEVER be tiny. Do you *need* 32-bit? What are you proposing to do with this slow CPU? -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
Reply by ●March 17, 20082008-03-17
Take a look at the "light 8080" at open cores.
The author made it very small. For fun I moved the registers into block
RAM (M4K)and nearly halved the size down to 230 LE on Cyclone 2.
There is enough documentation with the project to get you started.
+------------------------------------------------------------------------------+
; Fitter Summary
;
+------------------------------------+-----------------------------------------+
; Family ; Cyclone II
;
; Device ; EP2C20F484C7
;
; Timing Models ; Final
;
; Total logic elements ; 230 / 18,752 ( 1 % )
;
; Total combinational functions ; 227 / 18,752 ( 1 % )
;
; Dedicated logic registers ; 99 / 18,752 ( < 1 % )
;
; Total registers ; 99
;
; Total pins ; 74 / 315 ( 23 % )
;
; Total virtual pins ; 0
;
; Total memory bits ; 16,000 / 239,616 ( 7 % )
;
; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % )
;
; Total PLLs ; 0 / 4 ( 0 % )
;
+------------------------------------+-----------------------------------------+
climber.tim@gmail.com wrote:
> Hi.
> It's probably not very good place for asking such, but there're should
> be at least those who knows starting points.
> We need to design our own CPU which can be very slow. It can execute
> each instruction, let's say, up to 50 cycles. We don't care about
> speed, and we are also don't care about memory size for microcode, but
> we're really care about CPU unit size.
> Where to read about CPU designing techniques, which are about shifting
> all possible to microcode from CPU unit? Extreme case will be probably
> Turing machine, but it's not practical. CPU registers and instructions
> in our case should be looks like ARM9 processor, maybe.
Reply by ●March 17, 20082008-03-17
climber.tim@gmail.com wrote:> Hi. > It's probably not very good place for asking such, but there're should > be at least those who knows starting points. > We need to design our own CPU which can be very slow. It can execute > each instruction, let's say, up to 50 cycles. We don't care about > speed, and we are also don't care about memory size for microcode, but > we're really care about CPU unit size. > Where to read about CPU designing techniques, which are about shifting > all possible to microcode from CPU unit? Extreme case will be probably > Turing machine, but it's not practical. CPU registers and instructions > in our case should be looks like ARM9 processor, maybe.Sounds like homework ?. If you want simple, search for MC14500, which will give you a very small opcode set, to start from. If this is targeting FPGA, then better might be Mico8, PicoBlaze, or similar 8 bit variants. Also, if size matters more than speed, you could look at a core optimised to execute from SPI Serial memory, and you could map spare, non-hardcoded opcodes, into a jump table - that allows you to make up more opcodes in firmware. -jg
Reply by ●March 17, 20082008-03-17
On 17 Mrz., 10:20, sky46...@trline4.org wrote:> climber....@gmail.com wrote: > Instructions that you ought to have: > Shift left/rightYou do not need a left shift (add suffices) but the right shift is actually a necessary operation. To the OP: Read fpgacpu.org (outdated but good) Also see this: http://eis.eit.uni-kl.de/eis/teaching/practical/files/KapE.pdf http://eis.eit.uni-kl.de/~kolja/assembler.html Kolja Sulimma
Reply by ●March 17, 20082008-03-17
<climber.tim@gmail.com> wrote in message news:97c32a9f-aec1-4862-97dc-1fe6455f407c@m3g2000hsc.googlegroups.com...> Hi. > It's probably not very good place for asking such, but there're should > be at least those who knows starting points. > We need to design our own CPU which can be very slow. It can execute > each instruction, let's say, up to 50 cycles. We don't care about > speed, and we are also don't care about memory size for microcode, but > we're really care about CPU unit size. > Where to read about CPU designing techniques, which are about shifting > all possible to microcode from CPU unit? Extreme case will be probably > Turing machine, but it's not practical. CPU registers and instructions > in our case should be looks like ARM9 processor, maybe.I would suggest you check out the 16C54 from Microchip, very simple instruction set and you can find a number of free implementations on the web in both Verilog/VHDL. I my experience writing the software tools take far more time than writing a simply processor so try to use an existing instruction set. Good luck, Hans www.ht-lab.com
Reply by ●March 17, 20082008-03-17
On 17 Mrz., 13:16, "HT-Lab" <han...@ht-lab.com> wrote:> <climber....@gmail.com> wrote in message > > news:97c32a9f-aec1-4862-97dc-1fe6455f407c@m3g2000hsc.googlegroups.com... > > > Hi. > > It's probably not very good place for asking such, but there're should > > be at least those who knows starting points. > > We need to design our own CPU which can be very slow. It can execute > > each instruction, let's say, up to 50 cycles. We don't care about > > speed, and we are also don't care about memory size for microcode, but > > we're really care about CPU unit size. > > Where to read about CPU designing techniques, which are about shifting > > all possible to microcode from CPU unit? Extreme case will be probably > > Turing machine, but it's not practical. CPU registers and instructions > > in our case should be looks like ARM9 processor, maybe. > > I would suggest you check out the 16C54 from Microchip, very simple > instruction set and you can find a number of free implementations on the web > in both Verilog/VHDL. I my experience writing the software tools take far > more time than writing a simply processor so try to use an existing > instruction set. > > Good luck, > > Hanswww.ht-lab.comwell, there are well-known candidates for SMALL FPGA CPU, but for the following spec * 32 bit registers, say block of 16 (use 32 LUTRAM == 16 LUT/LC) * serialized can run from spi flash up to 320MBit with http://www.winbond.com/NR/rdonlyres/4C63AD62-967C-4B72-AF85-1F5984E8B199/0/W25Q80.pdf * can address large code space * can run at high fabric clocks (due to lack of parallel buses and parallel ALUs) now a bit-serialized CPU to the above spec can be done. it would use less than 100 slices. if anyone is willing to desing this CPU, I may have funds for it, really please... hm at 320MB/sec spi streaming, we get byte reads at 40Mhz from serial flash! so this serialized pico-cpu with less than 100 slices would outperform many 8 bit microcontrollers and 8 bit microprocessors of the past. And as the same flash could be used for FPGA config this 10 MIPS engine comes virtually free. pls do not suggest that picoblaze, or pic12 or i8080 can do this for this low fabric utilization Anttis
Reply by ●March 17, 20082008-03-17
"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message news:e0est356k8ji6osq2hhkmelcdkfebnhmtr@4ax.com...> On Mon, 17 Mar 2008 01:37:43 -0700 (PDT), climber.tim@gmail.com wrote: > > Do you *need* 32-bit? What are you proposing to do with this > slow CPU?.His homework. ;)
Reply by ●March 17, 20082008-03-17
"Antti" <Antti.Lukats@googlemail.com> wrote in message news:564d1032-a4bf-4615-b56e-8ec1ed31c7a8@f63g2000hsf.googlegroups.com...> > well, there are well-known candidates for SMALL FPGA CPU, but for the > following spec > > * 32 bit registers, say block of 16 (use 32 LUTRAM == 16 LUT/LC) > * serialized can run from spi flash up to 320MBit with > > http://www.winbond.com/NR/rdonlyres/4C63AD62-967C-4B72-AF85-1F5984E8B199/0/W25Q80.pdf > * can address large code space > * can run at high fabric clocks (due to lack of parallel buses and > parallel ALUs) > > now a bit-serialized CPU to the above spec can be done. > it would use less than 100 slices. > > if anyone is willing to desing this CPU, I may have funds for it, > really please... > > hm at 320MB/sec spi streaming, we get byte reads at 40Mhz from serial > flash! > > so this serialized pico-cpu with less than 100 slices would outperform > many > 8 bit microcontrollers and 8 bit microprocessors of the past. > > And as the same flash could be used for FPGA config this 10 MIPS > engine > comes virtually free. > > pls do not suggest that picoblaze, or pic12 or i8080 can do this for > this low fabric utilization > > Anttis >Hi Antti, How many LUTs in a slice? In other words, what is your target usage in terms of 4-LUTs? Thanks, Syms.
