dual clock fifo

I wish to design a FIFO to tansfer data from a high speed clock
domain(320 MHz) to low speed clock domain(40 Mhz). I dont wish to use
the cores available from any of the vendors.

Inputs =>
DataIn       // 16 bit data input that is latched in on the posedge of
clkHigh when Wen is high
Wen         // Write enable to strobe in the data into the register
Ren         // read enable strobe to let the reg know data was read
out of the DataOut register
clkHigh    // High speed clock for writing data in
clkLow    // low speed clock for reading data out

Outputs =>
DataOut    // 16 bit data out that is changed  to the next value (or
all low if nothing is yet stored inside) when Ren
                 goes low after toggling high based on the clkL
Full          // signal goes high when all input registers are filled
up.
Empty     // Goes high when nothing

How to decide on the depth of register DataOut to ensure that data is
not overwritten. The issue is that the FIFO has to have some high
speed storage capacity to allow for more data coming in then was
written out.

Any suggestions would be appreciated.

On Mar 17, 10:45=A0am, FPGA <FPGA.unkn...@gmail.com> wrote:
> I wish to design a FIFO to tansfer data from a high speed clock
> domain(320 MHz) to low speed clock domain(40 Mhz). I dont wish to use
> the cores available from any of the vendors.
>
> Inputs =3D>
> DataIn =A0 =A0 =A0 // 16 bit data input that is latched in on the posedge =
of
> clkHigh when Wen is high
> Wen =A0 =A0 =A0 =A0 // Write enable to strobe in the data into the registe=
r
> Ren =A0 =A0 =A0 =A0 // read enable strobe to let the reg know data was rea=
d
> out of the DataOut register
> clkHigh =A0 =A0// High speed clock for writing data in
> clkLow =A0 =A0// low speed clock for reading data out
>
> Outputs =3D>
> DataOut =A0 =A0// 16 bit data out that is changed =A0to the next value (or=

> all low if nothing is yet stored inside) when Ren
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0goes low after toggling high based on t=
he clkL
> Full =A0 =A0 =A0 =A0 =A0// signal goes high when all input registers are f=
illed
> up.
> Empty =A0 =A0 // Goes high when nothing
>
> How to decide on the depth of register DataOut to ensure that data is
> not overwritten. The issue is that the FIFO has to have some high
> speed storage capacity to allow for more data coming in then was
> written out.
>
> Any suggestions would be appreciated.

You need to know at what average and what burst rates you need to
design for, both filling and emptying the FIFO.  Without a limit on
the input fill rate, you need an infinite-sized FIFO.  So - figure out
your limits and design your FIFO based on max fill and min empty rate
conditions.  Otherwise, FIFOs *can* be straight-forward.  Synchronous
FIFOs are easier if the 320 MHz and 40 MHz domains are precisely
aligned but Gray code based FIFOs for asynchronous domains aren't too
much worse as long as you don't need to cut the delay for a new value
to the absolute minimum time possible; an extra clock of delay makes
things work beautifully.

- John_H

On Mar 17, 1:55=A0pm, John_H <newsgr...@johnhandwork.com> wrote:
> On Mar 17, 10:45=A0am, FPGA <FPGA.unkn...@gmail.com> wrote:
>
>
>
>
>
> > I wish to design a FIFO to tansfer data from a high speed clock
> > domain(320 MHz) to low speed clock domain(40 Mhz). I dont wish to use
> > the cores available from any of the vendors.
>
> > Inputs =3D>
> > DataIn =A0 =A0 =A0 // 16 bit data input that is latched in on the posedg=
e of
> > clkHigh when Wen is high
> > Wen =A0 =A0 =A0 =A0 // Write enable to strobe in the data into the regis=
ter
> > Ren =A0 =A0 =A0 =A0 // read enable strobe to let the reg know data was r=
ead
> > out of the DataOut register
> > clkHigh =A0 =A0// High speed clock for writing data in
> > clkLow =A0 =A0// low speed clock for reading data out
>
> > Outputs =3D>
> > DataOut =A0 =A0// 16 bit data out that is changed =A0to the next value (=
or
> > all low if nothing is yet stored inside) when Ren
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0goes low after toggling high based on=
 the clkL
> > Full =A0 =A0 =A0 =A0 =A0// signal goes high when all input registers are=
 filled
> > up.
> > Empty =A0 =A0 // Goes high when nothing
>
> > How to decide on the depth of register DataOut to ensure that data is
> > not overwritten. The issue is that the FIFO has to have some high
> > speed storage capacity to allow for more data coming in then was
> > written out.
>
> > Any suggestions would be appreciated.
>
> You need to know at what average and what burst rates you need to
> design for, both filling and emptying the FIFO. =A0Without a limit on
> the input fill rate, you need an infinite-sized FIFO. =A0So - figure out
> your limits and design your FIFO based on max fill and min empty rate
> conditions. =A0Otherwise, FIFOs *can* be straight-forward. =A0Synchronous
> FIFOs are easier if the 320 MHz and 40 MHz domains are precisely
> aligned but Gray code based FIFOs for asynchronous domains aren't too
> much worse as long as you don't need to cut the delay for a new value
> to the absolute minimum time possible; an extra clock of delay makes
> things work beautifully.
>
> - John_H- Hide quoted text -
>
> - Show quoted text -

The FIFO is 16 bits wide and 8 words deep. The purpose of using this
FIFO is for synchronization between the 2 clock domains.

On Mar 17, 11:03=A0am, FPGA <FPGA.unkn...@gmail.com> wrote:
> On Mar 17, 1:55=A0pm, John_H <newsgr...@johnhandwork.com> wrote:
>
>
>
>
>
> > On Mar 17, 10:45=A0am, FPGA <FPGA.unkn...@gmail.com> wrote:
>
> > > I wish to design a FIFO to tansfer data from a high speed clock
> > > domain(320 MHz) to low speed clock domain(40 Mhz). I dont wish to use
> > > the cores available from any of the vendors.
>
> > > Inputs =3D>
> > > DataIn =A0 =A0 =A0 // 16 bit data input that is latched in on the pose=
dge of
> > > clkHigh when Wen is high
> > > Wen =A0 =A0 =A0 =A0 // Write enable to strobe in the data into the reg=
ister
> > > Ren =A0 =A0 =A0 =A0 // read enable strobe to let the reg know data was=
 read
> > > out of the DataOut register
> > > clkHigh =A0 =A0// High speed clock for writing data in
> > > clkLow =A0 =A0// low speed clock for reading data out
>
> > > Outputs =3D>
> > > DataOut =A0 =A0// 16 bit data out that is changed =A0to the next value=
 (or
> > > all low if nothing is yet stored inside) when Ren
> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0goes low after toggling high based =
on the clkL
> > > Full =A0 =A0 =A0 =A0 =A0// signal goes high when all input registers a=
re filled
> > > up.
> > > Empty =A0 =A0 // Goes high when nothing
>
> > > How to decide on the depth of register DataOut to ensure that data is
> > > not overwritten. The issue is that the FIFO has to have some high
> > > speed storage capacity to allow for more data coming in then was
> > > written out.
>
> > > Any suggestions would be appreciated.
>
> > You need to know at what average and what burst rates you need to
> > design for, both filling and emptying the FIFO. =A0Without a limit on
> > the input fill rate, you need an infinite-sized FIFO. =A0So - figure out=

> > your limits and design your FIFO based on max fill and min empty rate
> > conditions. =A0Otherwise, FIFOs *can* be straight-forward. =A0Synchronou=
s
> > FIFOs are easier if the 320 MHz and 40 MHz domains are precisely
> > aligned but Gray code based FIFOs for asynchronous domains aren't too
> > much worse as long as you don't need to cut the delay for a new value
> > to the absolute minimum time possible; an extra clock of delay makes
> > things work beautifully.
>
> > - John_H- Hide quoted text -
>
> > - Show quoted text -
>
> The FIFO is 16 bits wide and 8 words deep. The purpose of using this
> FIFO is for synchronization between the 2 clock domains.- Hide quoted text=
 -
>
> - Show quoted text -

So if you know it's 8 words deep, what's the problem?  Is it that you
don't know how to design a FIFO from scratch since you don't want to
use a core?

Please specify if the domains are 100% synchronous or if they're
asynchronous.  If you can't guarantee phase alignment of the two
domains, consider it asynchronous.

Please verify that you want the empty flag on the read side and the
full on the write side.

Specify whether you're a VHDL or Verilog engineer.

What family and vendor is your FPGA?  Do you want to target a specific
memory type (such as CLB SelectRAM or M512 RAMs)?

You're no stranger to the board so this doesn't appear to be homework;
why avoid the cores?

- John_H

On Mar 17, 3:19=A0pm, John_H <newsgr...@johnhandwork.com> wrote:
> On Mar 17, 11:03=A0am, FPGA <FPGA.unkn...@gmail.com> wrote:
>
>
>
>
>
> > On Mar 17, 1:55=A0pm, John_H <newsgr...@johnhandwork.com> wrote:
>
> > > On Mar 17, 10:45=A0am, FPGA <FPGA.unkn...@gmail.com> wrote:
>
> > > > I wish to design a FIFO to tansfer data from a high speed clock
> > > > domain(320 MHz) to low speed clock domain(40 Mhz). I dont wish to us=
e
> > > > the cores available from any of the vendors.
>
> > > > Inputs =3D>
> > > > DataIn =A0 =A0 =A0 // 16 bit data input that is latched in on the po=
sedge of
> > > > clkHigh when Wen is high
> > > > Wen =A0 =A0 =A0 =A0 // Write enable to strobe in the data into the r=
egister
> > > > Ren =A0 =A0 =A0 =A0 // read enable strobe to let the reg know data w=
as read
> > > > out of the DataOut register
> > > > clkHigh =A0 =A0// High speed clock for writing data in
> > > > clkLow =A0 =A0// low speed clock for reading data out
>
> > > > Outputs =3D>
> > > > DataOut =A0 =A0// 16 bit data out that is changed =A0to the next val=
ue (or
> > > > all low if nothing is yet stored inside) when Ren
> > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0goes low after toggling high base=
d on the clkL
> > > > Full =A0 =A0 =A0 =A0 =A0// signal goes high when all input registers=
 are filled
> > > > up.
> > > > Empty =A0 =A0 // Goes high when nothing
>
> > > > How to decide on the depth of register DataOut to ensure that data i=
s
> > > > not overwritten. The issue is that the FIFO has to have some high
> > > > speed storage capacity to allow for more data coming in then was
> > > > written out.
>
> > > > Any suggestions would be appreciated.
>
> > > You need to know at what average and what burst rates you need to
> > > design for, both filling and emptying the FIFO. =A0Without a limit on
> > > the input fill rate, you need an infinite-sized FIFO. =A0So - figure o=
ut
> > > your limits and design your FIFO based on max fill and min empty rate
> > > conditions. =A0Otherwise, FIFOs *can* be straight-forward. =A0Synchron=
ous
> > > FIFOs are easier if the 320 MHz and 40 MHz domains are precisely
> > > aligned but Gray code based FIFOs for asynchronous domains aren't too
> > > much worse as long as you don't need to cut the delay for a new value
> > > to the absolute minimum time possible; an extra clock of delay makes
> > > things work beautifully.
>
> > > - John_H- Hide quoted text -
>
> > > - Show quoted text -
>
> > The FIFO is 16 bits wide and 8 words deep. The purpose of using this
> > FIFO is for synchronization between the 2 clock domains.- Hide quoted te=
xt -
>
> > - Show quoted text -
>
> So if you know it's 8 words deep, what's the problem? =A0Is it that you
> don't know how to design a FIFO from scratch since you don't want to
> use a core?
I am not sure if the design would change depending on whether the high
and low frequencies change.
>
> Please specify if the domains are 100% synchronous or if they're
> asynchronous. =A0If you can't guarantee phase alignment of the two
> domains, consider it asynchronous.
Asynchronous.
>
> Please verify that you want the empty flag on the read side and the
> full on the write side.
Yes
>
> Specify whether you're a VHDL or Verilog engineer.
Verilog
>
> What family and vendor is your FPGA? =A0Do you want to target a specific
> memory type (such as CLB SelectRAM or M512 RAMs)?
I dont want the design to be specific to a particular chip.
>
> You're no stranger to the board so this doesn't appear to be homework;
> why avoid the cores?
The cores are not getting simulated with Modelsim XE. And I would like
to design my own in either case.
>
> - John_H- Hide quoted text -
>
> - Show quoted text -

On Mar 17, 1:29=A0pm, FPGA <FPGA.unkn...@gmail.com> wrote:
<snip>
> And I would like to design my own in either case.
<snip>

So why are you asking us? ;-)

"FPGA" <FPGA.unknown@gmail.com> wrote in message 
news:b799694d-48d2-4ebb-92e4-0953385d8a52@b64g2000hsa.googlegroups.com...
>I wish to design a FIFO to tansfer data from a high speed clock
> domain(320 MHz) to low speed clock domain(40 Mhz). I dont wish to use
> the cores available from any of the vendors.

If I was you, I really would use a vendor-supplied core. Xilinx and Altera 
(and I suspect others) provide these free and they've been well tested in 
many, many designs. The port names may differ between different vendors but 
you can make the FIFO virtually vendor-agnostic by providing a trivial 
wrapper to name the ports as you wish. 

On Mar 17, 4:37=A0pm, "David Spencer" <davidmspen...@verizon.net> wrote:
> "FPGA" <FPGA.unkn...@gmail.com> wrote in message
>
> news:b799694d-48d2-4ebb-92e4-0953385d8a52@b64g2000hsa.googlegroups.com...
>
> >I wish to design a FIFO to tansfer data from a high speed clock
> > domain(320 MHz) to low speed clock domain(40 Mhz). I dont wish to use
> > the cores available from any of the vendors.
>
> If I was you, I really would use a vendor-supplied core. Xilinx and Altera=

> (and I suspect others) provide these free and they've been well tested in
> many, many designs. The port names may differ between different vendors bu=
t
> you can make the FIFO virtually vendor-agnostic by providing a trivial
> wrapper to name the ports as you wish.

If for some (strange) reason you want to roll your own,
 you face three challenges around the FULL flag:
You must detect FULL fast enough, within a 3 ns period.
And you must release FULL in response to a read clock, without getting
into metastable problems.
And you must compare the two counters without decoding glitches.
All this is stuff the we core designers have solved already for you,
at much higher speed...
Peter Alfke, Xilinx

HI,

I suggest u to once look into elastic buffers may be tht'll help
you...........

John_H wrote:
> On Mar 17, 1:29 pm, FPGA <FPGA.unkn...@gmail.com> wrote:
> <snip>
>> And I would like to design my own in either case.
> <snip>
> 
> So why are you asking us? ;-)

It looks like p171 of

http://www.google.com/url?sa=t&ct=res&cd=7&url=http%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DaQd4QYNV88EC%26pg%3DPA161%26lpg%3DPA161%26dq%3Dverilog%2Bfifo%2Bgray%26source%3Dweb%26ots%3DfY7n_OHYFN%26sig%3DkArkUjHVCE_M87AwKkrU61gWaz0%26hl%3Den&ei=rr3fR_qqJ5qMiwGyqZjRBQ&usg=AFQjCNGottyhGBvcjXugi1wBigp7dDB8wA&sig2=ormNgEQa4GqcdBc-ULwKxQ

has a reasonable FIFO.

I can't pull one of my FIFOs out of a work file and I did my taxes 
yesterday instead of throwing together a FIFO for you.

The flags shouldn't be a big problem for you if you're willing to wait 
an extra cycle for the Gray counters to settle out.  Having an empty on 
the read side means the empty de-asserts only when there's a word has 
long since settled in the buffer memory and asserts only in the read 
clock's domain.  Similarly with the full flag on the transmit side, the 
full asserts with the transmit clock but could be a clock worth of delay 
late for de-assertion due to the Gray count registration from the read 
domain to the write domain.

For a "complete" constraint set, the timing path from the point where 
the Gray count is registered in the new timing domain to where the 
values are used should be reduced by any metastability delay *or* 
registered twice.  It would be easy enough to reduce a 25ns period to 
23ns or less and not have any significant metastability issues but 
cutting down a 3125ps period by 2ns would be miserable.  For the 320 MHz 
domain, registering the Gray count twice would be a solid way to go.

Gray counters are pretty easy.  Handling metastability for these 
slow-acting flags is pretty straightforward.  What tends to get the 
designer is an incorrect FIFO size or a software guy that thinks the way 
to clear a FIFO is to just read n words rather than reading until the 
empty flag asserts.  If the hardware guy doesn't have past-end 
read/write handling in place, errant behavior will produce errants.

If after looking at the Google Books example you still aren't sure what 
to do, let us know.  I can cobble some Verilog together that I'll 
happily share, untested.

- John_H