vhdl type conversions

hi

can anybody help me out with my problem please:
i have a custom type:

type STATE_TYPE is (Idle, Read_Config, Read_Data, Generate_Address,
Generate_Strobe, Write_Data);
signal state        : STATE_TYPE;

for debugging purposes i want to route the signal state out of the
fpga. for that i have a
signal dbg_state std_logic_vector(2 downto 0) in my portmap.
but of course the statement dbg_state <=  state; does not work. i have
to do some type of typeconversion. i just cant find out how to do
that...
any ideas please ?

thanks

On Mar 19, 7:32 am, "u_stad...@yahoo.de" <u_stad...@yahoo.de> wrote:
> hi
>
> can anybody help me out with my problem please:
> i have a custom type:
>
> type STATE_TYPE is (Idle, Read_Config, Read_Data, Generate_Address,
> Generate_Strobe, Write_Data);
> signal state        : STATE_TYPE;
>
> for debugging purposes i want to route the signal state out of the
> fpga. for that i have a
> signal dbg_state std_logic_vector(2 downto 0) in my portmap.
> but of course the statement dbg_state <=  state; does not work. i have
> to do some type of typeconversion. i just cant find out how to do
> that...
> any ideas please ?
>
> thanks

Try:
case state is
	when Idle  	                => dbg_state <= "000";
	when Read_Config          => dbg_state <= "001";
	when Read_Data            => dbg_state <= "010";
	when Generate_Address => dbg_state <= "011";
	when Generate_Strobe   => dbg_state <= "100";
	when Write_Data  	  => dbg_state <= "101";
	when others 	             => NULL;
end case;

On Tue, 18 Mar 2008 14:32:08 -0700 (PDT), 
u_stadler@yahoo.de wrote:

>i have a custom type:
>
>type STATE_TYPE is (Idle, Read_Config, Read_Data, Generate_Address,
>Generate_Strobe, Write_Data);
>signal state        : STATE_TYPE;
>
>for debugging purposes i want to route the signal state out of the
>fpga. for that i have a
>signal dbg_state std_logic_vector(2 downto 0) in my portmap.
>but of course the statement dbg_state <=  state; does not work. i have
>to do some type of typeconversion. i just cant find out how to do
>that...
>any ideas please ?

(1) Try comp.lang.vhdl instead.
(2) Write a function to do the type conversion - it makes
    life far easier in the long run - and use a case statement
    inside that function:

  subtype slv3 is std_logic_vector(2 downto 0);
  function to_slv3(s: state_type) return slv3 is
  begin
    case s is
      when idle => return "000";
      when read_config => return "001";
      ....etc....
    end case;
  end;

And then you can simply drive the output...

  dbg_state <= to_slv3(state);

(3) Alternatively, make a lookup table.

  type state_dbg_lookup is array(state_type) of slv3;
  constant state_slv: state_dbg_lookup := (
    idle => "000",
    read_config => "001",
    ...
  );

  And then you can use that lookup table like a conversion function:

  dbg_state <= state_slv(state);


Conversion functions are nice because you can use them in
a port map - give the state machine a debug output port of
type "state_type", and wire a slv3 signal to that port...

   entity FSM_design is
     port (
       ...
       state_visibility: out state_type;
       ...
     );
   end;


   architecture A of thing_that_uses_FSM_design is
     ...
     signal state_dbg: slv3;
     ...
   begin
     ...
     FSM_instance: FSM_design port map (
       ...
       to_slv3(state_visibility) => state_dbg,
       ...
     );

Constant lookup tables are extremely efficient, and the code
for them is extremely easy to write and maintain, but you can't
use them in a port map as you can a conversion function.

HTH
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

u_stadler@yahoo.de wrote:

> type STATE_TYPE is (Idle, Read_Config, Read_Data, Generate_Address,
> Generate_Strobe, Write_Data);
> signal dbg_state std_logic_vector(2 downto 0) in my portmap.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
...
      function mode2vec (arg : STATE_TYPE)
         return std_logic_vector is
      begin
         return std_logic_vector(
            to_unsigned(STATE_TYPE'pos(arg),3)
            );
      end function mode2vec;
...
dbg_state <= mode2vec(state);

    -- Mike Treseler

<u_stadler@yahoo.de> wrote in message 
news:ca15b973-cf5a-4fba-bf44-a3161eee9238@e10g2000prf.googlegroups.com...
> hi
>
> can anybody help me out with my problem please:
> i have a custom type:
>
> type STATE_TYPE is (Idle, Read_Config, Read_Data, Generate_Address,
> Generate_Strobe, Write_Data);
> signal state        : STATE_TYPE;
>
> for debugging purposes i want to route the signal state out of the
> fpga. for that i have a
> signal dbg_state std_logic_vector(2 downto 0) in my portmap.
> but of course the statement dbg_state <=  state; does not work. i have
> to do some type of typeconversion. i just cant find out how to do
> that...

dbg_state <= std_logic_vector(to_unsigned(STATE_TYPE'pos(state), 3));

The 'pos attribute returns the 'position' within the enumerated type.  So 
STATE_TYPE'pos(Idle) = 0, STATE_TYPE'pos(Read_Config) = 1, etc.  This 
'position' is of type natural, which then gets converted to an unsigned and 
finally to a std_logic_vector.

As a side note, there is also a 'val attribute which converts an integer 
into the enumerated type (i.e. STATE_TYPE'val(2) = 'Read_Data'.  'val and 
'pos are inverse functions

Kevin Jennings 

On Tue, 18 Mar 2008 23:08:18 GMT, "KJ" wrote:

>dbg_state <= std_logic_vector(to_unsigned(STATE_TYPE'pos(state), 3));

Very nice, but in the past we have had trouble with some synthesis
tools not implementing 'pos and 'val.  Does anyone know the 
current state of play?  I know of several tools that *do* 
support it, but haven't done a thorough check recently.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message 
news:b3j0u313cagi92a8lih356oriesvtsb46e@4ax.com...
> On Tue, 18 Mar 2008 23:08:18 GMT, "KJ" wrote:
>
>>dbg_state <= std_logic_vector(to_unsigned(STATE_TYPE'pos(state), 3));
>
> Very nice, but in the past we have had trouble with some synthesis
> tools not implementing 'pos and 'val.  Does anyone know the
> current state of play?

'pos and 'val both work with Quartus, I'm pretty sure it works ISE and 
Synplify as well (or at least I don't remember opening any service requests 
to X and S about them not working).

I do seem to recall having a problem with 'succ with either ISE or Synplify, 
not sure which one and not sure what the state of that service request is. 
In any case, a problem with 'succ is not a problem with 'pos or 'val.

> I know of several tools that *do*
> support it, but haven't done a thorough check recently.

And apparently you don't want to name the several tools that you know that 
do support it even while asking others for that same info ;)

Kevin Jennings 

thanks for all the answers!
just tried it and yes it works in ise too!

Urban Stadler

u_stadler@yahoo.de wrote:
> thanks for all the answers!
> just tried it and yes it works in ise too!

Thanks for reporting the results.

    -- Mike Treseler

On Tue, 18 Mar 2008 23:31:09 GMT, "KJ" wrote:

[I wrote:]
>> I know of several tools that *do* support
[VHDL 'pos and 'val attributes]

>And apparently you don't want to name the several tools that you know that 
>do support it even while asking others for that same info ;)

No, indeed I don't.

If I say (truthfully) "tools A and B support feature F", and it
happens that tool C also supports feature F, then vendor C is
quite likely to give my employer a hard time for the perceived
unfair publicity.  I would much prefer to say "some tools support
feature F", and allow people to find out for themselves from
their chosen (or candidate) vendors if it matters to them.

If I were to get involved in "who supports what" feature comparisons,
I would be duty bound to be far more thorough and careful than would
ever be possible in a newsgroup posting.  In particular, I would need
to prepare my comparisons and submit them to all the vendors before
publication so that they could correct any factual inaccuracies 
before going to press.

I have no desire to be a stooge of any of the tool vendors, but
it is also very important to me and to my employer that we treat
them all fairly.  We cannot avoid discussing specific tools as
part of our training courses, and we must scrupulously avoid bias.  

By contrast, a customer of one single vendor has (almost) no such
obligation of impartiality and, give or take a few legalistic
constraints, can say whatever they want about the tool they 
have purchased.

Sorry to disappoint :-)
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.