Synoplify ???

Mike Treseler wrote:

>> The last design I tried on both (A V2-1K, 75% full, 50MHz) Synplify
>> Pro was 2 CLB's smaller and 5 Hz faster than XST.
> 
> Unfortunately for mentor, synplicity et. al.
> parity has been reached by some fpga vendors
> and vendor-independent synthesis licenses
> are much harder to justify than they once were.

The results are very design specific. I have seen in big timing critical
designs that the vendor-independent tools make better end results in
terms of density and clock frequency. Also the independent tools are
usually much better in inferring complex structures (they tend to
find memories in suprising places nowadays :))

Usually it's even hard to get designs that can be used with the two
major independent tools trough the vendors tools (due to unsupported
VHDL structures, not as good inferring etc.) So it is quite hard
to test the vendor tools without major hacking of the code.


--Kim

Kim Enkovaara wrote:

> The results are very design specific. I have seen in big timing critical
> designs that the vendor-independent tools make better end results in
> terms of density and clock frequency. Also the independent tools are
> usually much better in inferring complex structures (they tend to
> find memories in suprising places nowadays :))

I have seen this also in one tight design.
It is important to keep at least
one vendor-independent synthesis license
for this reason, and as check-off
item for the design and the design rules.

However, if I can fit a standard design and make
Fmax without tying up the fancy licenses,
the group is better off.

> Usually it's even hard to get designs that can be used with the two
> major independent tools trough the vendors tools (due to unsupported
> VHDL structures, not as good inferring etc.) So it is quite hard
> to test the vendor tools without major hacking of the code.

It is possible to construct synchronous design rules
that will pass the front ends of quartus, xst, mentor and synplicity.
It's when I bend the rules with an asynch vendor element like
a PLL or FIFO that testing is complicated.
Sometimes the design can be structured into
synchronous and asynchronous pieces.

             -- Mike Treseler